Message signaled interrupt redirection

• US 20060294277A1
• Filed: 06/24/2005
• Published: 12/28/2006
• Est. Priority Date: 06/24/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tetrick, Raymond Scott
• Application Number:
  US11/165,732
• Publication Number:
  US 20060294277A1
• Time in Patent Office: Days
• US Class Current: 710/269
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A method, device, and system are disclosed. In one embodiment, the method comprises receiving a message signaled interrupt, parsing an interrupt vector from the message signaled interrupt, locating an interrupt entry associated with the interrupt vector in a table of interrupt entries, and sending information associated with the interrupt entry to a processor.

Claims

1. A method, comprising:

receiving a message signaled interrupt;

parsing an interrupt vector from the message signaled interrupt;

locating an interrupt entry associated with the interrupt vector in a table of interrupt entries; and

sending information associated with the interrupt entry to a processor.

2. The method of claim 1, wherein the message signaled interrupt further comprises:

message address register contents; and

message data register contents including at least an interrupt vector field.

3. The method of claim 2, wherein parsing an interrupt vector from the message signaled interrupt comprises determining the information contained in the interrupt vector field of the message data register contents.

4. The method of claim 3, wherein the table of interrupt entries comprises a contiguous portion of a memory, wherein at least a portion of each interrupt entry includes a table entry vector.

5. The method of claim 4, wherein locating an interrupt entry associated with the interrupt vector in a table of interrupt entries comprises finding the interrupt entry in the table that has a corresponding table entry vector that matches the interrupt vector.

6. The method of claim 2, wherein the interrupt vector field comprises a 16-bit value.

7. The method of claim 4, wherein the contiguous portion of a memory comprises a contiguous portion of system main memory.

8. An apparatus, comprising:

a memory to store a table of interrupt entries; and

an interrupt redirection unit operable to receive a message signaled interrupt, parse an interrupt vector from the message signaled interrupt, locate an interrupt entry in the table associated with the interrupt vector, and send information associated with the interrupt entry to a processor.

9. The device of claim 8, wherein the message signaled interrupt further comprises:

message address register contents; and

message data register contents including at least an interrupt vector.

10. The device of claim 9, wherein the table of interrupt entries comprises a contiguous portion of a memory, wherein at least a portion of each interrupt entry includes a table entry vector.

11. The device of claim 10, wherein the interrupt redirection unit is further operable to search the table of interrupt entries for a table entry vector that matches the interrupt vector.

12. The device of claim 9, wherein the interrupt vector comprises a 16-bit value.

13. The device of claim 10, wherein the contiguous portion of a memory comprises a contiguous portion of system main memory.

14. A system, comprising:

an interconnect;

a processor coupled to the interconnect;

a network interface card coupled to the interconnect;

memory coupled to the interconnect, the memory to store a table of interrupt entries;

a secondary bus master device coupled to the interconnect, the secondary bus master device operable to send a message signaled interrupt across the interconnect; and

an interrupt redirection unit coupled to the interconnect, the interrupt redirection unit to receive a message signaled interrupt, to parse an interrupt vector from the message signaled interrupt, to locate an interrupt entry in the table associated with the interrupt vector, and to send information associated with the interrupt entry to a processor.

15. The system of claim 14, wherein the message signaled interrupt further comprises:

message address register contents; and

message data register contents including at least an interrupt vector.

16. The system of claim 15, wherein the table of interrupt entries comprises a contiguous portion of a memory, wherein at least a portion of each interrupt entry includes a table entry vector.

17. The system of claim 16, wherein the interrupt redirection unit is further operable to search the table of interrupt entries for a table entry vector that matches the interrupt vector.

18. The system of claim 15, wherein the interrupt vector comprises a 16-bit value.