Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same

• US 20070023833A1
• Filed: 06/15/2006
• Published: 02/01/2007
• Est. Priority Date: 07/28/2005
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nagoga, Mikhail, Okhonin, Serguei
• Application Number:
  US11/453,594
• Publication Number:
  US 20070023833A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. Circuitry, coupled to the electrically floating body transistor of the memory cell, (i) generates read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation. The electrically floating body transistor may be disposed on a bulk-type substrate or SOI-type substrate.

Claims

1. An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes;

a source region;

a drain region;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein the memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; and

circuitry, coupled to the electrically floating body transistor of the memory cell, to (i) generate read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; and

wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation.

2. The integrated circuit device of claim 1 wherein electrically floating body transistor is an N-channel type transistor.

3. The integrated circuit device of claim 1 wherein electrically floating body transistor is a P-channel type transistor.

4. The integrated circuit device of claim 1 wherein the read control signals include a signal applied to each of the gate and drain region to provide impact ionization in the body region of the electrically floating body transistor.

5. The integrated circuit device of claim 1 wherein the circuitry applies the read control signals to the electrically floating body transistor to sense the data state of the memory cell, wherein the read control signals include a signal applied to each of the gate and drain region to provide impact ionization in the body region of the electrically floating body transistor.

6. The integrated circuit device of claim 1 wherein electrically floating body transistor is disposed on bulk-type semiconductor substrate.

7. The integrated circuit device of claim 1 wherein electrically floating body transistor is disposed on SOI-type substrate.

8. The integrated circuit device of claim 1 wherein the circuitry includes sense amplifier circuitry and/or word line drivers.

9. The integrated circuit device of claim 1 wherein in response to the read control signals, the electrically floating body transistor replenishes more charge in the body region of the electrically floating body transistor when the transistor is in a first data state than when the transistor is in a second data state.

10. An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor includes;

a source region having impurities to provide a first conductivity type;

a drain region having impurities to provide the first conductivity type,

a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;

a gate spaced apart from the body region;

wherein the memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;

circuitry, coupled to the electrically floating body transistor of the memory cell, to (i) generate read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; and

wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation.

11. The integrated circuit device of claim 10 wherein electrically floating body transistor is an N-channel type transistor.

12. The integrated circuit device of claim 10 wherein electrically floating body transistor is a P-channel type transistor.

13. The integrated circuit device of claim 10 wherein the read control signals include a signal applied to each of the gate and drain region to provide impact ionization in the body region of the electrically floating body transistor.

14. The integrated circuit device of claim 10 wherein the circuitry applies the read control signals to the electrically floating body transistor to sense the data state of the memory cell, wherein the read control signals include a signal applied to each of the gate and drain region to provide impact ionization in the body region of the electrically floating body transistor.

15. The integrated circuit device of claim 10 wherein the substrate is a bulk-type semiconductor substrate.

16. The integrated circuit device of claim 10 wherein the substrate is an SOI-type substrate.

17. The integrated circuit device of claim 10 wherein the circuitry includes sense amplifier circuitry.

18. The integrated circuit device of claim 17 wherein the circuitry includes word line drivers.

19. The integrated circuit device of claim 10 wherein in response to the read control signals, the electrically floating body transistor replenishes more charge in the body region of the electrically floating body transistor when the transistor is in a first data state than when the transistor is in a second data state.