Phase change memory device and method of manufacturing the same

• US 20070025226A1
• Filed: 07/20/2006
• Published: 02/01/2007
• Est. Priority Date: 07/29/2005
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Park, Young, Lee, Seung, Choi, Kyu, Ryu, Sang, Lee, Nam, Yu, Byoung, Yoon, Sung
• Application Number:
  US11/490,405
• Publication Number:
  US 20070025226A1
• Time in Patent Office: Days
• US Class Current: 369/100
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

Provided are a phase change memory device and a method of fabricating the same capable of maximizing a contact area of a phase change layer and a heating electrode. The memory device includes a heating electrode and a phase change layer. The heating electrode covers at least one side exposed by a pore and a portion of a surface of a lower electrode and includes a recess region. The phase change layer is stacked on the heating electrode filling up the recess region. The memory device may maximize a contact area of the phase change layer and the heating electrode, thereby greatly reducing power consumption.

Claims

1. A phase change memory device comprising:

an insulating layer covering at least one surface of a lower electrode and including a pore that exposes a portion of the surface of the lower electrode;

a heating electrode covering at least one surface of the insulating layer and the portion of the surface of the lower electrode exposed by the pore, and the heating electrode including a recess region;

a phase change layer formed on the heating electrode and filled into the recess region; and

an upper electrode stacked on the phase change layer.

2. The phase change memory device of claim 1, wherein the insulating layer includes a plurality of pores formed on a surface of the lower electrode.

3. The phase change memory device of claim 1, wherein the heating electrode surrounds at least one surface of the phase change layer.

4. The phase change memory device of claim 1, wherein the heating electrode has a uniform thickness.

5. The phase change memory device of claim 1, wherein the heating electrode thickens toward a lower portion of a sidewall of the pore.

6. The phase change memory device of claim 1, wherein the heating electrode is formed of a combination of an electrode having a uniform thickness with an electrode thickening toward a lower portion of the pore.

7. The phase change memory device of claim 1, wherein at least one or more barrier layers are formed between the phase change layer and the upper electrode, and the barrier layer is at least one layer selected from a Ti layer, a TiAlN layer, a TiSiN layer, and a TiN layer.

8. A phase change memory device comprising:

an insulating layer including a pore that exposes a portion of a surface of a lower electrode;

a heating electrode covering at least one sidewall of the insulating layer and the portion of the surface of the lower electrode exposed by the pore, and the heating electrode including a recess region;

a phase change layer formed on the heating electrode and filled into the recess region; and

an upper electrode stacked on the phase change layer,

wherein at least one surface of the phase change layer is surrounded with the heating electrode that covers at least one sidewall of the insulating layer exposed by the pore.

9. A method of fabricating a phase change memory device, the method comprising:

forming a lower electrode;

forming an insulating layer covering at least one surface of the lower electrode;

etching the insulating layer to form a pore exposing a portion of a surface of the lower electrode;

forming a heating electrode that covers at least one sidewall of the pore and has a recess region; and

forming a phase change layer that fills up the recess region and is stacked on the heating electrode.

10. The method of claim 9, wherein the heating electrode surrounds at least one surface of the phase change layer.

11. The method of claim 9, wherein the heating electrode has a uniform thickness.

12. The method of claim 9, wherein the heating electrode thickens toward a lower portion of a sidewall of the pore.

13. The method of claim 9, wherein the heating electrode is formed of a combination of an electrode having a uniform thickness with an electrode thickening toward a lower portion of the pore.

14. The method of claim 9, wherein a heating electrode material layer is formed on the overall substrate including the insulating layer by using a blanket method and the heating electrode material layer is removed so that an upper surface of the insulating layer is exposed to form the heating electrode.

15. The method of claim 9, wherein a heating electrode material layer is formed on the overall substrate including the insulating layer by using a blanket method and the heating electrode material layer is etched by using a spacer etching method to form the heating electrode.

16. A method of fabricating a phase change memory device, the method comprising:

forming a lower electrode;

forming an insulating layer covering at least one surface of the lower electrode;

etching the insulating layer to form a pore exposing a portion of a surface of the lower electrode;

forming a heating electrode that covers at least one sidewall of the pore and has a recess region; and

forming a phase change layer that fills up the recess region and is stacked on the heating electrode,

wherein at least one surface of the phase change layer is surrounded with the heating electrode that covers at least one sidewall of the insulating layer exposed by the pore.