Semiconductor memory device

• US 20070051997A1
• Filed: 08/31/2005
• Published: 03/08/2007
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh, Haller, Gordon, Cummings, Steve
• Granted Patent: US 7,696,567 B2
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1. A memory device comprising:

a semiconductor substrate having a first surface;

a recessed gate formed in the substrate and defining a first and second lateral sides;

a first source/drain region formed on the first surface of the semiconductor substrate adjacent the first lateral side of the recessed gate;

a second source/drain region formed on the first surface of the semiconductor substrate adjacent the second lateral side of the recessed gate, wherein application of a voltage to the recessed gate results in formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

a charge storage device formed above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region; and

a conductive data line interposed between the charge storage device and the first surface of the semiconductor substrate wherein the conductive data line comprises a first portion that extends at a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically contact the second source/drain region, and wherein the first and second portions are formed of the same material.

2. The memory device of claim 1, wherein the conductive data line electrically couples to the charge storage device when the recessed gate is activated so as to transmit a signal indicative of a charge state of the charge storage device.

3. The memory device of claim 1, further comprising:

a dielectric plug positioned between the first portion of the conductive data line and the second source/drain region.

4. The memory device of claim 3, wherein the dielectric plug comprises silicon dioxide.

5. The memory device of claim 1, wherein the conductive data line comprises polysilicon.

6. The memory device of claim 1, wherein the conductive data line comprises one or more silicide layers.

7. The memory device of claim 1, wherein the charge storage device comprises a capacitor.

8. The memory device of claim 7, wherein the capacitor comprises

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

9. The memory device of claim 1, wherein the recessed gate is positioned substantially elevationally below the first and second source/drain regions so as to reduce the cross-capacitance between the recessed gate and the first and second source/drain regions.

10. A method of fabricating a memory device, the method comprising;

forming a semiconductor substrate having a first surface;

forming a recessed gate in the substrate, wherein the recessed gate defines a first and second lateral sides;

forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line comprises a first portion that extends a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically contact the second source/drain region, and wherein the first and second portions are formed of the same material; and

forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region.

11. A memory device comprising:

a semiconductor substrate;

a vertically extending gate region recessed in the substrate;

a source region positioned on a first side of the gate, the source region being formed at least partially in the semiconductor substrate;

a drain region positioned on a second side of the gate, wherein the second side is opposite the first side; and

a digit line contact directly electrically connected to the source region and directly electrically connected to a digit line contact of the memory device.

12. The memory device of claim 11, further comprising a charge storage device electrically coupled to the digit line contact, wherein, when the vertically extending gate is activated a signal indicative of a charge state of the charge storage device is transmitted on the digit line.

13. The memory device of claim 11, wherein the digit line contact comprises a first portion that extends a first height above a top surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically contact the source region.

14. A memory device comprising:

a source region,

a drain region,

a gate region separating the source and drain regions, and

means for directly electrically coupling a digit line electrode of the memory device to the source region.

15. The memory device of claim 14, wherein the gate region is positioned substantially elevationally below the source and drain regions so as to reduce the cross-capacitance between the gate region and the source and drain regions.

16. A memory array comprising a plurality of memory cells, the array comprising;

a semiconductor substrate having a first surface;

a plurality of recessed gates formed in the substrate, each defining respective first and second lateral sides;

a plurality of first source/drain regions formed on the first surface of the semiconductor substrate adjacent respective first lateral sides of each recessed gate;

a plurality of second source/drain regions formed on the first surface of the semiconductor substrate adjacent respective second lateral sides of each recessed gate, wherein application of a voltage to each gate results in the formation of a conductive channel between the respective first and second source/drain regions on either side of the gate along a path that is recessed into the semiconductor substrate;

a plurality of charge storage devices formed above the semiconductor substrate, wherein the charge storage devices are electrically coupled to respective first source/drain regions; and

a plurality of conductive data lines interposed between each the charge storage devices and the first surface of the semiconductor substrate, wherein the conductive data lines each comprise;

a first portion that extends at a first height above the first surface of the semiconductor substrate; and

a second portion that extends downward from the first portion to electrically contact the second source/drain region.

17. The memory array of claim 16, wherein the first and second portion of the conductive data lines are formed of the same material.

18. The memory array of claim 16, wherein the first and second portion of the conductive data lines comprise polysilicon.

19. A memory device comprising;

a semiconductor substrate having a first surface;

a recessed gate that is formed in the substrate so as to be spaced a first distance from the first surface, wherein the recessed gate defines a first and second lateral sides;

a first source/drain region formed on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

a second source/drain region formed on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate wherein the application of voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate and wherein the first distance is selected such that the gate structure is substantially located below the first and second source/drain regions so as to reduce the cross-capacitance between the gate and the first and second source/drain regions;

a charge storage device formed above the semiconductor substrate wherein the charge storage device is electrically coupled to the first source/drain region; and

a conductive data line interposed between the charge storage device and the first surface of the semiconductor substrate wherein the conductive data line electrically couples to the charge storage device when the gate is activated so as to transmit a signal indicative of the charge state of the charge storage device.

20. The memory device of claim 19, wherein the charge storage device comprises a capacitor.

21. The memory device of claim 20, wherein the capacitor comprises:

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

22. A memory device comprising:

a semiconductor substrate having a top surface;

an active area positioned on a first side of the gate, the active area being formed in the semiconductor substrate; and

a vertically extending gate positioned proximate the active area, wherein a top surface of the gate is elevationally below the top surface of the semiconductor substrate.

23. The memory device of claim 22, wherein the first and second source/drain regions are formed at least partially above a top surface of the semiconductor substrate and the gate is formed substantially below the top surface of the semiconductor substrate.