Semiconductor memory device

• US 7,696,567 B2
• Filed: 08/31/2005
• Issued: 04/13/2010
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh Dang, Haller, Gordon, Cummings, Steve
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US11/218,184
• Publication Number:
  US 20070051997A1
• Time in Patent Office: 1,686 Days
• Field of Search: 257/296, 257/302, 257/E27.096, 257/301, 257/E27.089, 257/330, 257/E21.655, 257/E29.26, 438/242
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1. A memory device comprising;

a recessed gate that is recessed in a semiconductor material, wherein the recessed gate has first and second lateral sides;

a first source/drain formed in the semiconductor material adjacent a first lateral side of the recessed gate, the first source/drain having an upper surface and a lower surface in the semiconductor material;

a second source/drain formed in the semiconductor material adjacent a second lateral side of the recessed gate, the second source/drain having an upper surface and a lower surface in the semiconductor material, wherein the application of voltage to the gate results in the formation of a conductive channel between the first and second source/drains along a path that is recessed into the semiconductor material;

a charge storage device formed above the semiconductor material, wherein the charge storage device is electrically coupled to the first source/drain; and

a conductive data line interposed between the charge storage device and the semiconductor material, the conductive data line being electrically coupled to the second source/drain, wherein an upper surface of the gate is elevationally below the first and second source/drain upper surfaces, the upper surface of the gate being elevationally closer to the second source/drain lower surface than to the second source/drain upper surface.

2. The memory device of claim 1, wherein the charge storage device comprises a capacitor.

3. The memory device of claim 2, wherein the capacitor comprises:

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

4. A memory device comprising:

first and second source/drains formed in a semiconductor material, the first source/drain having a bottom surface in the semiconductor material, the second source/drain region having a bottom surface in the semiconductor material; and

a vertically extending gate positioned proximate the first and second source/drains, wherein a top surface of the gate is elevationally below a top surface of the semiconductor material in regions in which the first and second source/drains are formed, the top surface of the gate being elevationally closer to each of the first and second source/drain bottom surfaces than to said top surface of the semiconductor material.

5. A memory device comprising:

a recessed gate having first and second lateral sides;

a first source/drain formed in a semiconductor material adjacent the first lateral side of the recessed gate, the first source/drain having an upper surface in the semiconductor material;

a second source/drain formed in the semiconductor material adjacent the second lateral side of the recessed gate, the second source/drain having an upper surface in the semiconductor material, wherein application of a voltage to the recessed gate results in formation of a conductive channel between the first source/drain and the second source/drain along a path that is recessed into the semiconductor material;

a charge storage device formed above the semiconductor material, wherein the charge storage device is electrically coupled to the first source/drain;

a conductive data line interposed between the charge storage device and the semiconductor material; and

a gate dielectric in contact with the recessed gate, the gate dielectric extending along a side of each of the first and second source/drains, the gate dielectric having an uppermost surface which is co-planar with the first source/drain upper surface and with the second source/drain upper surface.

6. A memory device comprising:

a vertically extending gate recessed in a semiconductor material;

a source positioned on a first side of the gate, the source being formed at least partially in the semiconductor material, the source having an upper surface in the semiconductor material;

a drain positioned on a second side of the gate, the drain being formed at least partially in the semiconductor material, wherein the second side is opposite the first side, the source having an upper surface in the semiconductor material;

a digit line electrically connected to the source; and

a gate dielectric in contact with the vertically extending gate, the gate dielectric extending along a side of each of the source and drain, the gate dielectric having an uppermost surface which is co-planar with the source upper surface and with the drain upper surface.