Non-volatile semiconductor memory device

• US 20070133277A1
• Filed: 11/21/2006
• Published: 06/14/2007
• Est. Priority Date: 11/29/2005
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kawai, Ken, Azuma, Ryotaro, Haruyama, Hoshihide, Suwa, Hitoshi, Kawahara, Akifumi
• Application Number:
  US11/602,272
• Publication Number:
  US 20070133277A1
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Claims

1. A non-volatile semiconductor memory device for performing data write and read operations in accordance with an input command, comprising:

a memory cell array including a plurality of memory cells having three or more threshold voltage distributions in a single electric charge accumulation portion; and

a program sequence control circuit for causing the memory cell to store each piece of data included in a data set composed of a plurality of data values, in association with any of the three or more threshold voltage distributions, and shifting a threshold voltage distribution used for data storage in one direction when a rewrite operation is performed with respect to the data stored in the memory cell, thereby performing a data rewrite operation.

2. The non-volatile semiconductor memory device of claim 1, wherein the program sequence control circuit causes the memory cell to store data in a manner which invariably associates the same data in the data set with a lowest or highest threshold voltage distribution of the three or more threshold voltage distributions.

3. The non-volatile semiconductor memory device of claim 2, wherein the program sequence control circuit causes the memory cell to store data using two consecutive threshold voltage distributions of the three or more threshold voltage distributions.

4. The non-volatile semiconductor memory device of claim 3, wherein, when a rewrite operation is performed with respect to data stored using an (n−

1)-th distribution (n;

a natural number) and a n-th distribution, the program sequence control circuit creates a state in which only the n-th distribution is used, before shifting a used threshold voltage distribution to an (n+1)-th distribution, depending on given data.

5. The non-volatile semiconductor memory device of claim 3, wherein, when a rewrite operation is performed with respect to data stored using an (n−

1)-th distribution (n;

a natural number) and a n-th distribution, the program sequence control circuit directly shifts used threshold voltage distributions to the n-th distribution and an (n+1)-th distribution, depending on given data.

6. The non-volatile semiconductor memory device of claim 2, wherein the data set is composed of binary data, and

the program sequence control circuit causes the memory cell to store the binary data using the three or more threshold voltage distributions.

7. The non-volatile semiconductor memory device of claim 6, wherein the program sequence control circuit fixedly associates one piece of data of the data set with the highest or lowest threshold voltage distribution, and when a rewrite operation is performed with respect to stored data, shifts a threshold voltage distribution in only a memory cell or memory cells which require transition to the highest or lowest threshold voltage distribution.

8. The non-volatile semiconductor memory device of claim 1, wherein the program sequence control circuit causes the memory cell to store data by associating a plurality of data sets with the three or more threshold voltage distributions.

9. The non-volatile semiconductor memory device of claim 8, wherein the data set is composed of binary data, and

the program sequence control circuit causes the memory cell to store the binary data in association with two consecutive threshold voltage distributions.

10. The non-volatile semiconductor memory device of claim 9, further comprising:

a preliminary write section for changing a memory cell in an n-th distribution state into an (n+1)-th distribution state; and

a data write section for shifting only a memory cell to which data different from data corresponding to an (n+1)-th distribution state is to be written, to an ((n+2)-th distribution.

11. The non-volatile semiconductor memory device of claim 8, wherein the data set is composed of binary data, and

the program sequence control circuit causes the memory cell to store the binary data using the three or more threshold voltage distributions.

12. The non-volatile semiconductor memory device of claim 11, wherein the program sequence control circuit, when rewriting data, shifts a threshold voltage distribution of only a memory cell or memory cells in which data is to be changed, to an upper level.

13. The non-volatile semiconductor memory device of claim 11, further comprising:

a data compression sequence control circuit for compressing the number of used distributions from a state in which three or more threshold voltage distributions are used in the memory cell array to a state in which two threshold voltage distributions which are an m-th threshold voltage distribution (m;

a natural number) and an (m+1)-th threshold voltage distribution are used, in the background, when an operation is not executed after a data rewrite operation is finished.

14. The non-volatile semiconductor memory device of claim 13, further comprising:

a distribution compression flag storing circuit for storing compression completion information indicating whether or not compression of the number of distributions performed by the data compression sequence control circuit has been completed; and

a read circuit for selecting any of a multi-level read mode in which a plurality of read determination levels are successively used to read data from the memory cell, and a single-level read mode in which a single read determination level is used to read data, based on the compression completion information stored in the distribution compression flag storing circuit, to read out data from the memory cell.

15. The non-volatile semiconductor memory device of claim 14, further comprising:

a determination level storing circuit for storing determination level information indicating a determination level which is used when data is read out from the memory cell; and

a power-ON sequence control circuit for causing the distribution compression flag storing circuit to store the compression completion information, and causing the determination level storing circuit to store the determination level information, when power is turned ON.

16. The non-volatile semiconductor memory device of claim 14, further comprising:

a determination level storing circuit for storing determination level information indicating a determination level which is used when data is read out from the memory cell;

a non-volatile distribution compression flag area for storing the compression completion information;

a non-volatile determination level memory area for storing the determination level information; and

a power-ON sequence control circuit for writing the compression completion information stored in the distribution compression flag area into the distribution compression flag storing circuit, and writing the determination level information stored in the determination level memory area into the determination level storing circuit, after the data compression sequence control circuit compresses the number of distributions,

wherein the data compression sequence control circuit stores the compression completion information into the distribution compression flag area, and the determination level information into the determination level memory area, after compressing the number of distributions.

17. The non-volatile semiconductor memory device of claim 1, further comprising:

a determination level storing circuit for storing determination level information indicating a determination level which is used when data is read out from the memory cell; and

a power-ON sequence control circuit for selecting a determination level to be used to read data by performing a read operation with respect to each memory cell, and causing the determination level storing circuit to store the determination level as the determination level information.

18. The non-volatile semiconductor memory device of claim 17, further comprising:

a non-volatile used distribution position storing area for storing threshold voltage distribution position information indicating a position of a threshold voltage distribution used in the memory cell,

wherein the power-ON sequence control circuit causes the determination level storing circuit to store determination level information in association with the threshold voltage distribution position information stored in the used distribution position storing area.

19. The non-volatile semiconductor memory device of claim 17, further comprising:

a monitor bit having the same structure as that of the memory cell, for invariably storing the same data,

wherein the power-ON sequence control circuit performs a read operation with respect to the monitor bit to specify the position of the threshold voltage distribution, and causes the determination level storing circuit to store determination level information obtained, depending on the specified position.

20. The non-volatile semiconductor memory device of claim 1, further comprising:

an initialization sequence control circuit for shifting a threshold voltage distribution to be used for data storage in a direction opposite to a shift direction when a data write operation is performed so that data stored in each memory cell corresponds to a threshold voltage distribution successively from a lowest threshold voltage distribution or a highest threshold voltage distribution,

wherein the data set is composed of binary data.

21. The non-volatile semiconductor memory device of claim 20, further comprising:

a transition completion flag indicating completion of shifting in a direction in which the threshold voltage distribution increases, when a threshold voltage distribution having a maximum usable voltage is used.

22. The non-volatile semiconductor memory device of claim 20, wherein the initialization sequence control circuit performs the initialization operation in the background when waiting for an input of the command.

23. The non-volatile semiconductor memory device of claim 1, further comprising:

a write section having a first write function of performing a write operation with respect to each piece of write data to target a first write level when rewriting data stored in the memory cell, and a function of performing a write operation with respect to each piece of write data to target a second write level which is different from the first write level, when rewriting data stored in the memory cell; and

a write level selection section for selecting any one of the first write level and the second write level for each data write operation.

24. The non-volatile semiconductor memory device of claim 23, further comprising:

a determination section for determining data written by the first write function;

a data holding section for holding the data determined by the determination section; and

a long-term guaranteeing write operation section for performing an additional write operation using the data held by the data holding section.

25. The non-volatile semiconductor memory device of claim 23, further comprising:

a write function determining flag indicating, after data is written by the first write function, that the written data is data written by the first write function.

26. The non-volatile semiconductor memory device of claim 24, wherein the long-term guaranteeing write operation section performs the additional write operation in the background when waiting for an input of the command.

27. The non-volatile semiconductor memory device of claim 23, further comprising:

an initialization sequence control circuit for shifting a threshold voltage distribution to be used for data storage in a direction opposite to a shift direction when a data write operation is performed so that data stored in each memory cell corresponds to a threshold voltage distribution successively from a lowest threshold voltage distribution,

wherein the data set is composed of binary data.

28. The non-volatile semiconductor memory device of claim 27, wherein the initialization sequence control circuit performs the initialization in the background when waiting for an input of the command.

29. The non-volatile semiconductor memory device of claim 1, further comprising:

an erase completion flag indicating whether or not data in the memory cell is an erased state,

wherein the program sequence control circuit, when causing the memory cell to be in the erased state, rewrites the erase completion flag so that the erase completion flag indicates that the memory cell is in the erased state, without rewriting the data in the memory cell.

30. The non-volatile semiconductor memory device of claim 29, further comprising:

an initialization sequence control circuit for initializing the memory cell into the erased state in units of a sector,

wherein, during initialization, the initialization sequence control circuit searches for a free sector having a smallest number of times of an erase operation, swaps data in a sector to be initialized with data in the free sector having the smallest number of times of an erase operation, and initializes the free sector having the smallest number of times of an erase operation.

31. The non-volatile semiconductor memory device of claim 30, wherein, during initialization, when there is a plurality of free sectors having the smallest number of times of an erase operation, the initialization sequence control circuit searches for a position of a highest threshold voltage distribution, and swaps data in a sector having a lowest highest threshold voltage distribution with data in the sector requiring initialization.

32. The non-volatile semiconductor memory device of claim 29, wherein the initialization sequence control circuit searches for a position of a highest threshold voltage distribution, swaps data in the sector requiring initialization with data in a sector having a lowest highest threshold voltage distribution, and initializes the sector having the lowest highest threshold voltage distribution.

33. The non-volatile semiconductor memory device of claim 32, wherein, during initialization, when there are a plurality of lowest highest threshold voltage distributions, the initialization sequence control circuit searches the number of times of an erase operation, and swaps data in a sector having a smallest number of times of an erase operation with data in a sector to be initialized.

34. The non-volatile semiconductor memory device of claim 1, further comprising:

a data address management table for storing information indicating an area in the memory cell array,

wherein the program sequence control circuit fixes data in the area indicated by the information stored in the data address management table.

35. The non-volatile semiconductor memory device of claim 25, wherein the long-term guaranteeing write operation section performs the additional write operation in the background when waiting for an input of the command.