Dynamic Array Architecture

• US 20070210391A1
• Filed: 03/07/2007
• Published: 09/13/2007
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Smayling, Michael C., Becker, Scott T.
• Granted Patent: US 7,446,352 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 2027/11812 4-T CMOS basic cell
• CPC Class Codes: H01L 2027/11814 5-T CMOS basic cell
• CPC Class Codes: H01L 2027/11855 Twin-tub technology
• CPC Class Codes: H01L 2027/11861 Substrate and well contacts
• CPC Class Codes: H01L 2027/11862 Horizontal or vertical grid line density
• CPC Class Codes: H01L 2027/11864 Yield or reliability
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of diffusion regions defined within the substrate, the plurality of diffusion regions separated from each other by a non-active region of the substrate; and

a plurality of linear gate electrode tracks defined to extend over the substrate in a single common direction, each linear gate electrode track defined by one or more linear gate electrode segments, wherein each of the plurality of linear gate electrode tracks that extends over both a diffusion region and a non-active region of the substrate is defined such that a separation distance between ends of adjacent linear gate electrode segments therein is minimized while ensuring adequate electrical isolation between the adjacent linear gate electrode segments, wherein the linear gate electrode segments are defined to have variable lengths to enable logic gate functionality.

2. A semiconductor device as recited in claim 1, wherein the substrate is a silicon substrate.

3. A semiconductor device as recited in claim 1, wherein the substrate is a silicon-on-insulator substrate.

4. A semiconductor device as recited in claim 1, wherein each of the plurality of diffusion regions is defined to have a two-dimensionally varying shape with respect to a plane coincident with a top surface of the substrate.

5. A semiconductor device as recited in claim 1, wherein a number of diffusion region bend topologies is limited such that in a lithographic process light interaction between bends in the each of the plurality of diffusion regions and one or more overlying linear gate electrode segments is predictable.

6. A semiconductor device as recited in claim 1, wherein each linear gate electrode segment is defined to have a length that extends in a single direction over the substrate and have a substantially consistent vertical cross-section shape along its length.

7. A semiconductor device as recited in claim 1, wherein the plurality of linear gate electrode tracks and the one or more linear gate electrode segments therein are defined to be parallel with respect to each other.

8. A semiconductor device as recited in claim 1, wherein a center-to-center separation distance between adjacent linear gate electrode tracks is defined to optimize constructive interference of light waves in a lithographic process so as to minimize lithographic correction required to render a mask for use in fabricating the one or more linear gate electrode segments within the plurality of linear gate electrode tracks.

9. A semiconductor device as recited in claim 8, wherein the lithographic correction includes one or both of optical proximity correction and reticle enhancement techniques.

10. A semiconductor device as recited in claim 1, wherein one or more of the linear gate electrode segments is defined to extend through a cell boundary to enable bridging between neighboring cells.

11. A semiconductor device as recited in claim 1, wherein the plurality of linear gate electrode tracks is defined such that each separation between ends of adjacent linear gate electrode segments in a given linear gate electrode track is offset from a separation between ends of adjacent linear gate electrode segments in an adjacent linear gate electrode track.

12. A semiconductor device as recited in claim 1, wherein a common separation distance between ends of adjacent linear gate electrode segments is utilized within each linear gate electrode track.

13. A semiconductor device as recited in claim 1, further comprising:

a plurality of interconnect layers defined above the plurality of linear gate electrode tracks, each of the plurality of interconnect layers including a plurality of linear conductor tracks defined to extend over the substrate in a single common direction within a given interconnect layer, each linear conductor track defined by one or more linear conductor segments, wherein each of the plurality of linear conductor tracks is defined such that a separation distance between ends of adjacent linear conductor segments therein is minimized while ensuring adequate electrical isolation between the adjacent linear conductor segments.

14. A semiconductor device as recited in claim 13, wherein each linear conductor segment in a given interconnect layer is defined to have a length that extends in a single direction over the substrate and have a substantially consistent vertical cross-section shape along its length.

15. A semiconductor device as recited in claim 13, wherein the plurality of linear conductor tracks and the one or more linear conductor segments therein within a given interconnect layer are defined to be parallel with respect to each other.

16. A semiconductor device as recited in claim 13, wherein a center-to-center separation distance between adjacent linear conductor tracks is defined to optimize constructive interference of light waves in a lithographic process so as to minimize lithographic correction required to render a mask for use in fabricating the one or more linear conductor segments within the plurality of linear conductor tracks.

17. A semiconductor device as recited in claim 13, wherein the plurality of linear conductor tracks is defined such that each separation between ends of adjacent linear conductor segments in a given linear conductor track is offset from a separation between ends of adjacent linear conductor segments in an adjacent linear conductor track.

18. A semiconductor device as recited in claim 13, wherein a common separation distance between ends of adjacent linear conductor segments is utilized within each linear conductor track in a given interconnect layer.

19. A semiconductor device as recited in claim 13, wherein the plurality of linear conductor tracks in a given interconnect layer are defined to extend over the substrate so as to cross the plurality of linear conductor tracks within an adjacent interconnect layer.

20. A semiconductor device as recited in claim 19, wherein linear conductor tracks in adjacent interconnect layers cross each other in a substantially perpendicular manner.

21. A semiconductor device as recited in claim 13, wherein the plurality of linear conductor tracks in a first interconnect layer above the plurality of linear gate electrode tracks is defined to extend over the substrate so as to cross the plurality of linear gate electrode tracks in a substantially perpendicular manner.

22. A semiconductor device as recited in claim 13, further comprising:

a plurality of diffusion contacts defined to connect the plurality of diffusion regions to selected linear conductor segments within the plurality of interconnect layers.

23. A semiconductor device as recited in claim 22, wherein a center-to-center separation distance between adjacent diffusion contacts is essentially equivalent to a center-to-center separation distance between adjacent linear gate electrode tracks, and wherein a center of each of the plurality of diffusion contacts is defined at a location corresponding to essentially a midpoint between adjacent linear gate electrode tracks.

24. A semiconductor device as recited in claim 13, further comprising:

a plurality of gate electrode contacts defined to connect the linear gate electrode segments that extend over a diffusion region to selected linear conductor segments within the plurality of interconnect layers.

25. A semiconductor device as recited in claim 24, wherein each of the plurality of gate electrode contacts is defined to have a linear shape, the linear shape defined by a length and a substantially consistent vertical cross-section shape along the length, wherein each of the plurality of gate electrode contacts is oriented such that its length extends in a single direction substantially perpendicular to an underlying linear gate electrode track.

26. A semiconductor device as recited in claim 25, wherein the length of each of the plurality of gate electrode contacts is sufficiently long so as to overlap an underlying linear gate electrode segment.

27. A semiconductor device, comprising:

a substrate;

a plurality of diffusion regions defined in the substrate to define active regions for transistor devices;

a plurality of linear gate electrode segments oriented in a common direction over the substrate, wherein a number of the plurality of linear gate electrode segments is disposed over a diffusion region, wherein each of the plurality of linear gate electrode segments that is disposed over the diffusion region includes a necessary active portion defined over the diffusion region and a uniformity extending portion defined to extend over the substrate beyond the diffusion region, wherein the plurality of linear gate electrode segments are defined to have variable lengths to enable logic gate functionality; and

a plurality of linear conductor segments disposed within a level over the plurality of gate electrode segments so as to cross the common direction of the plurality of gate electrode segments in a substantially perpendicular direction, wherein the plurality of linear conductor segments is defined to minimize an end-to-end spacing between adjacent linear conductor segments within a common line over the substrate.

28. A semiconductor device as recited in claim 27, wherein each of the plurality of diffusion regions is defined to have a two-dimensionally varying shape with respect to a plane coincident with a top surface of the substrate.

29. A semiconductor device as recited in claim 27, wherein a center-to-center separation distance between adjacent linear gate electrode segments is defined to optimize constructive interference of light waves in a lithographic process so as to minimize lithographic correction required to render a mask for use in fabricating the one or more linear gate electrode segments.

30. A semiconductor device as recited in claim 27, wherein the plurality of linear gate electrode segments is defined to minimize an end-to-end spacing between adjacent linear gate electrode segments within a common line over the substrate.

31. A semiconductor device as recited in claim 30, wherein each end-to-end spacing between adjacent linear gate electrode segments in a given line across the substrate is offset from an end-to-end spacing between adjacent linear gate electrode segments in a next line across the substrate.

32. A semiconductor device as recited in claim 30, wherein a common end-to-end spacing distance is used between adjacent linear gate electrode segments.

33. A semiconductor device as recited in claim 27, wherein a center-to-center separation distance between adjacent linear conductor segments is defined to optimize constructive interference of light waves in a lithographic process so as to minimize lithographic correction required to render a mask for use in fabricating the one or more linear conductor segments.

34. A semiconductor device as recited in claim 27, further comprising:

a plurality of interconnect layers each of which includes a plurality of linear conductor segments defined to extend over the substrate so as to cross the plurality of linear conductor segments within an adjacent layer.

35. A gate electrode contact, comprising:

a linear conductive segment having a length and a substantially uniform cross-sectional shape along its length, the linear conductive segment oriented to have its length extend in a direction substantially perpendicular to an underlying gate electrode over which the linear conductive segment is disposed, the length of the linear conductive segment is defined to be larger than a width of the underlying gate electrode such that the linear conductive segment overlaps the underlying gate electrode.

36. A gate electrode contact as recited in claim 35, wherein the length of the linear conductive segment is defined to accommodate lithographic distortion of the linear conductive segment while maintaining an overlap of an entirety of the width of the underlying gate electrode.

37. A gate electrode contact as recited in claim 35, wherein a width of the linear conductive segment is substantially equivalent to the width of the underlying gate electrode.

38. A gate electrode contact as recited in claim 35, wherein the linear conductive segment is formed of polysilicon.

39. A contact layout, comprising:

a plurality of contacts defined on a common grid projected across a substrate; and

a number of sub-resolution contacts defined on the common grid to surround each of the plurality of contacts, each of the sub-resolution contacts defined to avoid their rendering in a lithographic process while reinforcing resolution of the contacts.

40. A contact layout as recited in claim 39, wherein the number of sub-resolution contacts are defined to occupy each gridpoint location on the common grid that is not occupied by one of the plurality of contacts.

41. A contact layout as recited in claim 39, wherein a shape of each sub-resolution contact is defined to optimize lithographic reinforcement of a neighboring contact.

42. A contact layout as recited in claim 39, wherein one or more sub-resolution contacts are defined to have an “

X”

shape to provide lithographic reinforcement to corner portions of a neighboring contact.

43. A contact layout as recited in claim 39, wherein the number of sub-resolution contacts are defined on the common grid to enable use of a phase shift masking technique to facilitate avoidance of sub-resolution contact rendering in a lithographic process.