MULTI-THREAD GRAPHICS PROCESSING SYSTEM

• US 20070222787A1
• Filed: 05/09/2007
• Published: 09/27/2007
• Est. Priority Date: 09/29/2003
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Morein, Stephen, Lefebvre, Laurent, Gruber, Andrew
• Granted Patent: US 7,742,053 B2
• Time in Patent Office: Days
• US Class Current: 345/522
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Claims

1. In a graphics processing system, a method for selecting a command thread for processing, the method comprising:

selecting a command thread from either of a plurality of pixel command threads and a plurality of vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads; and

providing the command thread to a command processing engine.

2. The method of claim 1, wherein selecting the command thread based on the relative priorities further comprises selecting the command thread based on specific commands that have been executed in any of the plurality of pixel command threads or any of the plurality of vertex command threads.

3. The method of claim 1, wherein selecting the command thread based on the relative priorities further comprises selecting the command thread based on specific commands that have yet to be executed in any of the plurality of pixel command threads or any of the plurality of vertex command threads.

4. The method of claim 1, wherein selecting the command thread based on the relative priorities further comprises selecting, as the command thread an oldest one of the plurality of pixel command threads and the plurality of vertex command threads.

5. The method of claim 1, wherein providing the command thread to the command processing engine further comprises, when the command thread is a pixel command thread from the plurality of pixel command threads, interleaving the command thread with at least one vertex command thread of the plurality of vertex command threads and, when the command thread is a vertex command thread from the plurality of vertex command threads, interleaving the command thread with at least one pixel command thread of the plurality of pixel command threads.

6. The method of claim 1, wherein selecting the command thread further comprises selecting a pixel command thread of the plurality of pixel command threads as the command thread without regard to ordering of the plurality of pixel command threads.

7. The method of claim 1, wherein selecting the command thread further comprises selecting a vertex command thread of the plurality of vertex command threads as the command thread without regard to ordering of the plurality of vertex command threads.

8. In a graphics processing system, a method for ensuring maximum utilization of a plurality of command processing engines, the method comprising:

receiving, by an arbiter, a plurality of pixel command threads and a plurality of vertex command threads for execution by the plurality of command processing engines; and

providing, by the arbiter, selected ones of the plurality of pixel command threads and the plurality of vertex command threads to any of the plurality of command processing engines for execution.

9. The method of claim 8, wherein providing the selected ones of the plurality of pixel command threads and the plurality of vertex command threads further comprises interleaving the selected ones of the plurality of pixel command threads and the plurality of vertex command threads.

10. The method of claim 8, further comprising providing the selected ones of the plurality of pixel command threads and the plurality of vertex command threads based on availability of the plurality of command processing engines.

11. A graphics processing system comprising:

at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads; and

an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads.

12. The graphics processing system of claim 11, further comprising:

a command processing engine, coupled to the arbiter, wherein the arbiter is further operable to provide the command thread to the command processing engine.

13. The graphics processing system of claim 11, wherein the first portion of the at least one memory device comprises a first memory device and the second portion of the at least one memory device comprises a second memory device.

14. The graphics processing system of claim 11, wherein a single memory device comprises the first portion and the second portion of the at least one memory device.

15. A graphics processing system comprising:

at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads;

an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads; and

a plurality of command processing engines, coupled to the arbiter, each operable to receive and process the command thread.

16. The graphics processing system of claim 15, wherein the plurality of command processing engines comprises at least one arithmetic logic unit.

17. The graphics processing system of claim 15, wherein the plurality of command processing engines comprises at least one texture processing engine.

18. The graphics processing system of claim 15, wherein the first portion of the at least one memory device comprises a first memory device and the second portion of the at least one memory device comprises a second memory device.

19. The graphics processing system of claim 15, wherein a single memory device comprises the first portion and the second portion of the at least one memory device.