SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP

• US 20070236232A1
• Filed: 06/14/2007
• Published: 10/11/2007
• Est. Priority Date: 08/25/2003
• Status: Abandoned Application

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Steinbrueck, Gary, Pakdaman, Nader, Vickers, James, Aghababazadeh, Majid, Estabil, Jose
• Application Number:
  US11/763,001
• Publication Number:
  US 20070236232A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. An assembly for evaluating a fabrication of a semiconductor wafer, wherein the semiconductor wafer includes one or more test structures positioned on wafer at various locations including within at least one die of the wafer, and wherein the assembly comprises:

one or more energy sources located externally to the semiconductor wafer;

a control system that is configured to control the one or more energy sources into directing energy onto one or more energy receiving elements on one or more die of the wafer, wherein the energy is suitable to activate the one or more test structures;

a detector system comprising one or more detectors, the detector system being configured to measure electrical activity from the one or more test structures that are activated by the direction of energy from the one or more energy sources in order to determine a performance parameter value for each of the one or more test structures;

a data processing unit that interprets electrical activity detected by the detector system and identifies a correlation between the performance parameter value and one or more fabrication steps or sequences of the fabrication.

2. The assembly of claim 1, wherein the assembly is configured to operate when the test structures are disposed on the wafer in a partially-fabricated state.

3. The assembly of claim 2, wherein the data processing unit determines a variance of the performance parameter value for multiple test structures located in the plurality of locations.

4. The assembly of claim 3, wherein the variance identifies one or more process variations in the fabrication.

5. The assembly of claim 1, wherein the detector system includes a photon detector that is configured to detect photons from the one or more test structures when the one or more test structures are activated.

6. The assembly of claim 5, wherein the photon detector is configured to detect photons emitted from a gate of a transistor that forms at least a part of the one or more test structures.

7. The assembly of claim 1, wherein the detector system includes a radio-frequency detector that detects a radio-frequency transmission that is converted from an output of the one or more test structures.

8. The assembly of claim 1, wherein the detector system includes an electron-beam that detects secondary electron emissions that are modulated by the output of the one or more test structures.

9. The assembly of claim 1, wherein the control system receives a feedback from the chip on the sufficiency of the energy from the one or more energy sources.

10. The assembly of claim 1, wherein the control system adjusts the energy directed from the one or more energy sources in response to receiving the feedback.

11. The assembly of claim 1, wherein the one or more energy sources includes a first laser that is configured to produce a modulating beam and a second laser that is configured to produce a constant beam.

12. The assembly of claim 1, wherein the performance parameter value is based on a signal delay.

13. The assembly of claim 1, wherein the control system is configured to control the one or more energy sources into causing the generation of a test signal and a power signal from within the die.