PARALLEL DATA PROCESSING APPARATUS

• US 20080028184A1
• Filed: 05/29/2007
• Published: 01/31/2008
• Est. Priority Date: 04/09/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Winser, Paul, McConnell, Ray, Rhoades, John, Cameron, Ken, Faulds, Gordon, David, Russell, Greer, Trey, Atkin, Phil, Stuttard, Dave, Day, Tim, Williams, Dave, O'Dea, Eamon
• Granted Patent: US 8,169,440 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Claims

1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, the method using a plurality of processing elements in parallel with one another, and comprising the steps of:

assigning respective vertex data to the processing elements;

on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data; and

transferring processed vertex data between processing elements so as to assemble primitive data.

2. A method as claimed in claim 1, wherein at least one processing element stores data relating to at least one of the geometrical primitives.

3. A method as claimed in claim 1, wherein each processing element stores data relating to at least on geometrical primitive.

4. A method as claimed in claim 1, wherein the processing elements are arranged in a single instruction multiple data (SIMD) array.

5. A method as claimed in claim 1, wherein the processing elements are arranged in a plurality of single instruction multiple data (SIMD) arrays.

6. A method as claimed in claim 1, wherein the processing elements are arranged in a single instruction multiple data (SIMD) array, the array being operable to process a plurality of instruction threads in parallel with one another.

7. A method as claimed in claim 1, wherein the processing elements are arranged in a plurality of single instruction multiple data (SIMD) arrays, the arrays being operable to process a plurality of instruction threads in parallel with one another.

8. A method as claimed in claim 1, wherein the processed vertex data is transferred between processing elements using direct inter-processing element connections.

9. A method as claimed in claim 1, wherein the processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.

10. A graphical data processing apparatus comprising a plurality of parallel processing elements, and a controller operable to assign respective vertex data to the processing elements, which vertex data relates to geometrical primitives, wherein each processing element is operable to perform at least one processing step on vertex data to produce processed vertex data, and wherein the controller is operable to cause processed image data to be transferred between processing elements so as to assemble primitive data.

11. An Apparatus as claimed in claim 10, wherein the controller is operable to cause at least one processing element to store data relating to at least one of the geometrical primitives.

12. An apparatus as claimed in claim 10, wherein the controller is operable to cause each processing element to store data relating to at least one geometrical primitive.

13. An apparatus as claimed in claim 10, wherein the processing elements are arranged in a single instruction multiple data (SIMD) array.

14. An apparatus as claimed in claim 10, wherein the processing elements are arranged in a plurality of single instruction multiple data (SIMD) arrays.

15. An apparatus as claimed in claim 10, wherein the processing elements are arranged in a single instruction multiple data (SIMD) array, the array being operable to process a plurality of instruction threads in parallel with one another.

16. An apparatus as claimed in claim 10, wherein the processing elements are arranged in a plurality of single instruction multiple data (SIMD) arrays, the arrays being operable to process a plurality of instruction threads in parallel with one another.

17. An apparatus as claimed in claim 10, comprising direct inter-processing element connections for transfer of processed vertex data therebetween.

18. An apparatus as claimed in claim 10, wherein the processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.