Parallel data processing apparatus
First Claim
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1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, and comprising the steps of:
- using a plurality of single instruction multiple data (SIMD) processing arrays to process the data, wherein each SIMD array comprises a plurality of processing elements configured to process data in parallel with each another;
wherein processing the data comprises,assigning respective vertex data to the processing elements, andon each processing element, performing at least one processing step on vertex data to produce processed vertex data,using a linear expression evaluator (LEE) circuit, which is coupled to each SIMD processing array in the plurality of SIMD processing arrays, to evaluate a linear expression,wherein the linear expression is of the form axi+byi+c, wherein xi and yi are variables associated with pixels, and a, b and c are coefficients,wherein the LEE is coupled to each SIMD processing array through a feedback bus, which enables data to flow from each processing element in the SIMD to the LEE and back to processing element, andwherein the feedback bus includes a feedback buffer (FBB) to store the coefficients a, b and c.
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Abstract
A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.
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12 Claims
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1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, and comprising the steps of:
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using a plurality of single instruction multiple data (SIMD) processing arrays to process the data, wherein each SIMD array comprises a plurality of processing elements configured to process data in parallel with each another; wherein processing the data comprises, assigning respective vertex data to the processing elements, and on each processing element, performing at least one processing step on vertex data to produce processed vertex data, using a linear expression evaluator (LEE) circuit, which is coupled to each SIMD processing array in the plurality of SIMD processing arrays, to evaluate a linear expression, wherein the linear expression is of the form axi+byi+c, wherein xi and yi are variables associated with pixels, and a, b and c are coefficients, wherein the LEE is coupled to each SIMD processing array through a feedback bus, which enables data to flow from each processing element in the SIMD to the LEE and back to processing element, and wherein the feedback bus includes a feedback buffer (FBB) to store the coefficients a, b and c. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A graphical data processing apparatus comprising:
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a plurality of single instruction multiple data (SIMD) processing arrays, wherein each SIMD array comprises a plurality of processing elements configured in parallel with one another such that each SIMD array is operable to process a plurality of instruction threads in parallel with one another, and a controller operable to assign respective vertex data to the processing elements, which vertex data relates to geometrical primitives, wherein each processing element is operable to perform at least one processing step on vertex data to produce processed vertex data, wherein the controller is operable to assemble primitive data by causing processed image data to be transferred between processing elements; and a linear expression evaluator (LEE) circuit coupled to each SIMD processing array in the plurality of SIMD processing arrays, wherein the LEE is configured to evaluate a linear expression of the form axi+byi+c, wherein xi and yi are variables associated with pixels, and a, b and c are coefficients, wherein the LEE is coupled to each SIMD processing array through a feedback bus, which enables data to flow from each processing element in the SIMD to the LEE and back to processing element, and wherein the feedback bus includes a feedback buffer (FBB) to store the coefficients a, b and c. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification