SYSTEMS AND METHODS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM

• US 20080034148A1
• Filed: 08/01/2006
• Published: 02/07/2008
• Est. Priority Date: 08/01/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., VanStee, Dustin J., Love, Carl E.
• Granted Patent: US 7,493,439 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

Claims

1. A memory system for storing and retrieving data for a processing system, the memory system comprising:

a memory controller for receiving and responding to memory access requests;

a plurality of memory devices;

a memory bus in communication with the memory controller; and

a memory hub device in communication with the memory bus, the memory hub device comprising;

a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus;

a memory device interface for communicating with the memory devices; and

a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

2. The memory system of claim 1 wherein the reporting includes outputting one or more of downstream utilized bus bandwidth, upstream utilized bus bandwidth, average read latency, and read to write bandwidth ratio.

3. The memory system of claim 1 wherein the performance monitor includes an event counter array for logging selected events detected in one or more of the address, control and data information.

4. The memory system of claim 3 wherein the selected events include one or more of read commands, write commands and responses to read commands.

5. The memory system of claim 3 wherein the performance monitor loads one or more entries in the event counter array into an event frequency array after one or more of a defined period of time has elapsed or an event count threshold has been reached.

6. The memory system of claim 5 wherein the performance monitor further resets the event counter array and increments an event frequency array load pointer.

7. The memory system of claim 1 wherein the performance monitor includes a bin counter for logging an elapsed time between related events.

8. The memory system of claim 7 wherein the related events include a read command and a response to the read command.

9. The memory system of claim 7 wherein the performance monitor transfers one or more entries in the bin counter into an event frequency array after one or more of a defined period of time has elapsed or an event count threshold has been reached.

10. The memory system of claim 9 wherein the performance monitor further resets the bin counter and increments an event frequency array load pointer.

11. The memory system of claim 1 wherein the performance monitor includes a trace array for recording one or more of the address, control and data information over time.

12. The memory system of claim 11 wherein the performance monitor sets thresholds on event counters and bin counters, and the trace array is stopped when one or more of these thresholds is exceeded, thereby stopping the trace array upon indication of an unexpected event occurring.

13. The memory system of claim 1 wherein the memory system is a determinate memory system.

14. The memory system of claim 1 wherein the memory system is an indeterminate memory system.

15. The memory system of claim 1 wherein performance monitor data is read by one or more reporting buses.

16. A memory subsystem comprising:

a plurality of memory devices; and

a memory hub device in communication with a memory bus, the memory hub device comprising;

a memory interface for transferring one or more of address, control and data information between the memory hub device and a memory controller via a memory bus;

a memory device interface for communicating with the memory devices; and

a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during subsystem operation.

17. The memory subsystem of claim 16 wherein the performance monitor includes one or more of an event counter array for logging selected events detected in one or more of the address, control and data information and a bin counter for logging an elapsed time between related events detected in one or more of the address, control and data information, and the performance monitor loads one or more of entries in the event counter array and entries in the bin counter into an event frequency array after one or more of a defined period of time has elapsed or an event count threshold has been reached.

18. The memory system of claim 16 wherein the performance monitor includes one or more trace arrays for recording one or more of the address, control and data information over time.

19. A memory controller for receiving and responding to memory access requests, the memory controller comprising:

a memory interface for transferring one or more of address, control and data information between the memory controller and one or more hub devices via a memory bus; and

a performance monitor for monitoring and reporting one or more of memory bus utilization and performance characteristics over defined intervals during system operation.

20. A memory hub device comprising:

a memory interface for transferring one or more of address, control and data information between the memory hub device and a memory controller via a memory bus;

a memory device interface for communicating with memory devices; and

a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during subsystem operation.

21. The memory hub device of claim 20 wherein the performance monitor includes one or more of an event counter array for logging selected events detected in one or more of the address, control and data information and a bin counter for logging an elapsed time between related events detected in one or more of the address, control and data information, and the performance monitor loads one or more of entries in the event counter array and entries in the bin counter into an event frequency array after one or more of a defined period of time has elapsed or an event count threshold has been reached.

22. The memory hub device of claim 21 wherein the performance monitor data is read using one or more reporting buses.

29. The method of claim 21 further comprising generating utilization statistics and performance characteristics in response to contents of the event frequency array.

30. The method of claim 22 further comprising outputting the contents of the one or more trace arrays.

23. A method of providing performance monitoring, the method comprising;

detecting the occurrence of selected events in a hub device, the events characterized by type;

recording the number of detected events of each type and elapsed time between any related events;

continuing the detecting and recording for a defined period of time or until an event count threshold has been reached; and

storing the recorded data in an event frequency array after the defined period of time or the event count threshold has been reached.

24. The method of claim 23 further comprising executing one or more trace arrays to record one or more of address, control and data information received by the memory hub device over time.

25. The method of claim 24 wherein the executing in the trace arrays is stopped when a pre-selected counter value is exceeded, thereby stopping the trace array upon indication of an unexpected event occurring.

26. The method of claim 23 wherein the memory system is determinate.

27. The method of claim 23 wherein the memory system is indeterminate.

28. The method of claim 23 further comprising outputting contents of the event frequency array.