Semiconductor devices, assemblies and constructions, and methods of forming semiconductor devices, assemblies and constructions

• US 20080048298A1
• Filed: 08/28/2006
• Published: 02/28/2008
• Est. Priority Date: 08/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yang, Xiawan, Taylor, Ted
• Granted Patent: US 7,537,994 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Claims

1. A method of forming semiconductor devices, comprising:

forming a pair of openings into a semiconductor material, the openings being spaced from one another by a segment of the semiconductor material;

forming liners along sidewalls of the openings; and

isotropically etching semiconductor material from the bottoms of the lined openings to merge the openings and thereby completely undercut said segment.

2. The method of claim 1 wherein the formation of the openings and undercutting of the segment forms a cavity extending beside and under the segment, and further comprising filling the cavity with electrically insulative material.

3. The method of claim 2 wherein the filling the cavity with electrically insulative material comprises filling the cavity with an electrically insulative material comprising silicon dioxide.

4. The method of claim 2 wherein the filling the cavity with electrically insulative material comprises filling the cavity with an electrically insulative material consisting of silicon dioxide.

5. The method of claim 1 wherein the formation of the openings and undercutting of the segment forms a cavity extending beside and under the segment, and further forming wordline material within the cavity and around the segment.

6. The method of claim 5 wherein the wordline material is formed to comprise one or more of compositions selected from the group consisting of metal, metal-containing compounds, and conductively-doped semiconductor material.

7. The method of claim 5 wherein the wordline material is formed to comprise conductively-doped silicon, and wherein the conductively-doped silicon is formed by:

initially depositing silicon within the cavity; and

after depositing the silicon, implanting conductive-enhancing dopant into the silicon.

8. The method of claim 5 wherein the wordline material is formed to comprise conductively-doped silicon, and wherein the conductively-doped silicon is formed by in situ doping silicon as the silicon is deposited within the cavity.

9. A method of forming semiconductor devices, comprising:

defining a plurality of active area locations within a semiconductor material, adjacent active area locations being spaced from one another by regions of the semiconductor material;

etching into the regions of the semiconductor material to form cavities extending completely under the active area locations; and

filling the cavities with dielectric material.

10-16. -16. (canceled)

17. A method of forming semiconductor devices, comprising:

providing a semiconductor material;

defining an array of active area locations within the semiconductor material, the array comprising columns and rows;

forming trenches between columns of the active area locations, the trenches extending to ends of the active area locations;

filling the trenches with a first dielectric material to form lines of the first dielectric material, the lines of first dielectric material and rows of active area locations defining a lattice;

sections of the semiconductor material being at locations between the rows and lines of the lattice, such sections alternating with active area locations along the columns of the array;

etching into the sections of semiconductor material to form openings which alternate with the active area locations along the columns of the array;

forming protective material along sidewalls of the openings to narrow the openings;

isotropically etching the semiconductor material through the narrowed openings to extend the openings completely under the active area locations; and

filling the openings with second dielectric material.

18-23. -23. (canceled)

24. A method of forming semiconductor devices, comprising:

providing a semiconductor material having a line location associated therewith, the line location having a pair of opposing sides;

anisotropically etching a pair of trenches into the semiconductor material on opposing sides of the line location;

isotropically etching the semiconductor material through the trenches to merge the trenches under at least a portion of the line location; and

forming electrically conductive gate material within the trenches and under at least a portion of the line location.

25-29. -29. (canceled)

30. A method of forming a transistor, comprising:

providing a semiconductor material;

defining a line across the semiconductor material, the line having a narrow region between wide regions, the line having a pair of opposing sides;

forming a pair of trenches along opposing sides of the line;

forming protective material along sidewalls of the trenches to narrow the trenches;

isotropically etching the semiconductor material through the trenches to merge the trenches under the narrow region without merge the trenches under the wide regions;

forming gate dielectric along the narrow region of the line; and

forming electrically conductive gate material within the trenches and under the narrow region.

31-35. -35. (canceled)

36. A semiconductor construction, comprising:

a base;

an array of semiconductor material active areas supported by the base, the array comprising columns and rows of the active areas;

lines of first insulative material along the columns of the active areas, the lines directly contacting ends of the active areas;

the lines of first insulative material and rows of the active areas defining a lattice;

sections of second insulative material at locations between the rows and lines of the lattice, such sections alternating with active areas along the columns of the array; and

regions of the second insulative material under the active areas;

individual regions extending from sections on opposing sides of individual active areas to entirely separate the individual active areas from the base.

37. The construction of claim 36 wherein the base comprises monocrystalline silicon, and wherein the active areas also comprise monocrystalline silicon.

38. The construction of claim 37 further comprising transistor gates over the active areas, and conductively-doped source/drain regions within the active areas;

the transistor gates and source/drain regions together forming transistors associated with the active areas.

39. The construction of claim 36 wherein the first insulative material consists of silicon dioxide.

40. The construction of claim 36 wherein the second insulative material consists of silicon dioxide.

41. The construction of claim 36 wherein the first insulative material and the second insulative material are of a common composition relative to one another.

42. The construction of claim 41 wherein the first and second insulative materials consist of silicon dioxide.

43. A semiconductor device, comprising:

a line of semiconductor material, the line having a narrow region between wide regions;

dielectric material entirely around the narrow region;

gate material extending entirely around the narrow region, and being spaced form the narrow region of the line by the dielectric material;

a channel region within the narrow region of the line; and

a pair of source/drain regions within the wide regions of the line and spaced from one another by the channel region.

44-45. -45. (canceled)

46. A semiconductor assembly, comprising:

a line of semiconductor material, the line having a narrow regions between wide regions;

the wide regions comprising source/drain regions of transistors and the narrow regions comprising channels between the source/drain regions;

first dielectric material entirely around the narrow regions;

transistor gate material extending entirely around the narrow region, and spaced form the narrow region of the line by the dielectric material; and

second dielectric material extending through the wide regions of the line and separating adjacent wide regions from one another.

47. (canceled)

48. An electronic system, comprising:

a processor;

memory in communication with the processor through addressing and read circuitry; and

wherein at least one of the memory and the processor comprises a transistor which includes;

a line of semiconductor material, the line having a narrow region between wide regions;

dielectric material entirely around the narrow region;

gate material extending entirely around the narrow region, and being spaced form the narrow region of the line by the dielectric material;

a channel region within the narrow region of the line; and

a pair of source/drain regions within the wide regions of the line and spaced from one another by the channel region.

49-50. -50. (canceled)