SELF-TIMED MEMORY HAVING COMMON TIMING CONTROL CIRCUIT AND METHOD THEREFOR
First Claim
1. A memory comprising:
- a memory array having a plurality of memory cells;
an address decoder for selecting a memory cell in response to an address;
a data input/output circuit for transmitting data to or from the selected memory cell;
a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an operation of the address decoder and the data input/output circuit during an access to the memory array; and
a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal.
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Accused Products
Abstract
A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.
25 Citations
20 Claims
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1. A memory comprising:
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a memory array having a plurality of memory cells; an address decoder for selecting a memory cell in response to an address; a data input/output circuit for transmitting data to or from the selected memory cell; a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an operation of the address decoder and the data input/output circuit during an access to the memory array; and a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory comprising:
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a memory array having a plurality of memory cells; a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access operation to the memory array; a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal; and a recovery circuit comprising a second latch, the second latch coupled to the first latch, the second latch receiving a recovery signal, the recovery signal being asserted in response to completion of the access operation to the memory array, wherein the second latch is for restoring the first latch to an initial condition in response to the recovery signal, and wherein the restoring of the first latch to the initial condition is independent of the clock signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method comprising:
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providing a memory having a memory array with a plurality of memory cells; coupling a clock signal to the memory; providing a plurality of clock driver circuits for timing an access to the memory array in response to a predetermined edge of the clock signal; and providing a latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to the first predetermined edge of the clock signal. - View Dependent Claims (18, 19, 20)
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Specification