PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE

• US 20080135874A1
• Filed: 01/16/2008
• Published: 06/12/2008
• Est. Priority Date: 07/23/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Divakaruni, Ramachandra, CHENG, Kangguo
• Granted Patent: US 9,515,140 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

Claims

1. A method, comprising:

forming a pattern of strained material and relaxed material on a substrate;

forming a strained device in the strained material; and

forming a non-strained device in the relaxed material.

2. The method of claim 1, wherein the step of forming the pattern of strained material and relaxed material on the substrate further comprises:

forming a buffer layer on the substrate, the buffer layer having a lattice constant/structure mismatch with the substrate;

forming a relaxed layer on the buffer layer;

forming a recess through the relaxed layer and the buffer layer, the recess having sidewalls;

forming the relaxed material in the recess; and

forming the strained material on the relaxed layer outside the confines of the recess, the strained material having a lattice constant/structure mismatch with the relaxed layer.

3. The method of claim 2, further comprises forming an insulating layer on the sidewalls before forming the relaxed layer in the recess.

4. The method of claim 2, wherein the relaxed layer and the buffer layer are selected from the group consisting of silicon carbon (SiC), silicon germanium (SiGe), Al_X1Ga_X2In_X3As_Y1P_Y2N_Y3Sb_Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1, and Zn_A1Cd_A2Se_B1Te_B2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1.

5. The method of claim 2, wherein the step of forming the buffer layer further comprises epitaxially growing multiple layers of a material forming the buffer layer such that the material forming the buffer layer has a base concentration proximate the substrate and an increased bench-mark concentration proximate the relaxed layer.

6. The method of claim 5, wherein the step of forming the relaxed layer further comprises epitaxially growing multiple layers of a material forming the relaxed layer such that the material forming the relaxed layer has a second base concentration proximate the buffer layer that approximately equals the benchmark concentration of the buffer layer material.

7. The method of claim 1, wherein the strained material is formed of carbon-doped silicon or germanium doped silicon.

8. The method of claim 1, wherein a buffer layer and a relaxed layer are disposed between the strained material and the substrate.

9. The method of claim 1, wherein the strained material is a semiconductor material doped by carbon or germanium.

10. An electrical device, comprising:

a pattern of strained material and relaxed material formed on a substrate;

a first device formed in the strained material; and

a second device formed in the relaxed material.

11. The electrical device of claim 10, further comprising:

a buffer layer formed in contact with a portion of a substrate, the buffer layer having a lattice constant/structure mismatch with the substrate;

a relaxed layer formed on the buffer layer;

a strained material formed on a top surface of the relaxed layer, wherein the relaxed layer places the strained material in one of a tensile or a compressive state; and

a non-strained material patterned proximate the strained material.

12. The electrical device of claim 11, wherein the first device formed in the strained material is a logic device and the second device formed in the non-strained material is a defect-sensitive device.

13. The electrical device of claim 11, wherein the relaxed material comprises a material which has a lattice constant/structure mismatch with the strained material.

14. The electrical device of claim 11, wherein the buffer layer and the relaxed layer are selected from the group consisting of silicon carbon (SiC), silicon germanium (SiGe), Al_X1Ga_X2In_X3As_Y1P_Y2N_Y3Sb_Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1, and Zn_A1Cd_A2Se_B1Te_B2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1.

15. The electrical device of claim 11, wherein a material forming the buffer layer increases in concentration from a base concentration proximate the substrate to a benchmark concentration proximate the relaxed layer.

16. The electrical device of claim 11, wherein the strained material is a carbon doped semiconductor material or a germanium doped semiconductor material.

17. The electrical device of claim 10, further comprising:

a second strained material formed proximate the strained material and the non-strained material, wherein the strained material is in a tensile or compressive state and the second strained material is in a compressive or tensile state, respectively.

18. The electrical device of claim 10, wherein the strained material is a carbon doped material or a germanium doped material.

19. The electrical device of claim 10, further comprising:

a recess formed in the substrate, the recess having side-walls, wherein the strained material is formed within the confines of the sidewalls and is a carbon doped material or a germanium doped material.

20. The electrical device of claim 19, wherein the sidewalls have an insulating layer and the strained material is formed within the confines of the insulating layer.