Demodulator, Chip And Method For Digital Demodulating An Fsk Signal

• US 20080169872A1
• Filed: 01/21/2005
• Published: 07/17/2008
• Est. Priority Date: 01/22/2004
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Ghovanloo, Maysam, Najafi, Khalil
• Granted Patent: US 7,881,409 B2
• Time in Patent Office: Days
• US Class Current: 329/300
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence

Abstract

A demodulator, chip and method for digitally demodulating an FSK signal utilizing a digital data transfer protocol and a digital demodulator circuit have been developed. The data-rate approaches the carrier-frequency. The one application for this technique is in the magnetically powered wireless systems such as biomedical implants and radio frequency identification (RFID) tags with high data rates above 1 Mbps. The demodulator circuit extracts the serial data bit-stream and a constant-frequency clock from an FSK carrier signal in the 1˜20 MHZ range, which can power the wireless system as well. The digital demodulator circuit is implemented entirely with digital circuitry and is called a digital-FSK (DFSK) demodulator.

Claims

1. In a high data rate receiver for an FSK data transmission system having a data transfer protocol, a digital demodulator for demodulating an FSK signal having a data rate from a carrier signal having a pair of carrier frequencies, the digital demodulator generating a serial data bit stream based on the FSK carrier signal and generating a synchronized constant frequency clock signal from the carrier frequencies based on the data transfer protocol for sampling the serial data bit stream wherein both the data transfer protocol and the demodulator are fully digital to make the system robust.

2. The demodulator as claimed in claim 1, wherein the data rate is greater than one million bits per second.

3. The demodulator as claimed in claim 1, wherein the data rate approximates the carrier frequencies.

4. The demodulator as claimed in claim 1, wherein the carrier frequency is less than about 25 megahertz and more than about 1 megahertz.

5. The demodulator as claimed in claim 1, wherein one of the carrier frequencies is approximately twice the other carrier frequency so that a duration of each data bit is substantially the same, independent of its value.

6. The demodulator as claimed in claim 1, wherein the demodulator also detects an error in the FSK carrier signal based on the protocol and provides a corresponding error signal.

7. The demodulator as claimed in claim 1, wherein the demodulator also digitally measures the period of each received positive half cycle of the FSK carrier signal to obtain a series of pulses which distinguish between long and short FSK carrier cycles.

8. The demodulator as claimed in claim 7, wherein the demodulator includes an n-bit counter that runs with a clock time-base, f_TB, having a substantially constant frequency at a rate substantially higher than the FSK carrier frequencies, f₁ and f₀, to digitally measure the periods.

9. The demodulator as claimed in claim 1, wherein the system is a magnetically powered wireless system.

10. The demodulator as claimed in 9, wherein the receiver is a wireless biomedical implant.

11. An FSK demodulator chip for an FSK data transmission system having a fully digital data transfer protocol, the chip comprising:

a substrate; and

a digital demodulator formed on the substrate for demodulating an FSK signal having a data rate from a carrier signal having a pair of carrier frequencies wherein the demodulator generates a serial data bit stream based on the FSK carrier signal and generates a synchronized constant frequency clock signal from the carrier frequencies based on the data transfer protocol for sampling the serial data bit stream and wherein the demodulator is fully digital to minimize the amount of surface area occupied by the demodulator on the substrate.

12. The chip as claimed in claim 11, wherein the data rate is greater than one million bits per second.

13. The chip as claimed in claim 11, wherein the data rate approximates the carrier frequencies.

14. The chip as claimed in claim 11, wherein the carrier frequency is less than about 25 megahertz and more than about 1 megahertz.

15. The chip as claimed in claim 11, wherein one of the carrier frequencies is approximately twice the other carrier frequency so that a duration of each data bit is substantially the same, independent of its value.

16. The chip as claimed in claim 11, wherein the demodulator also detects an error in the FSK carrier signal based on the protocol and provides a corresponding error signal.

17. The chip as claimed in claim 11, wherein the demodulator also digitally measures the period of each received positive half cycle of the FSK carrier signal to obtain a series of pulses which distinguish between long and short FSK carrier cycles.

18. The chip as claimed in claim 17, wherein the demodulator includes an n-bit counter that runs with a clock time-base f_TB, having a substantially constant frequency at a rate substantially higher than the FSK carrier frequencies, f₁ and f₀, to digitally measure the periods.

19. The chip as claimed in claim 11, wherein the system is a magnetically powered wireless system.

20. A method for demodulating an FSK signal having a data rate from a carrier signal having a pair of carrier frequencies in an FSK transmission system having a digital data transfer protocol, the method comprising:

digitally measuring the period of each received positive half cycle of the FSK carrier signal to obtain a series of pulses which distinguish between long and short FSK carrier cycles;

digitally generating a serial data bit stream based on the FSK carrier signal and the series of pulses; and

digitally generating a synchronized constant frequency clock signal from the carrier frequencies based on the digital data transfer protocol and the series of pulses.