Multi-Processor Flash Memory Storage Device and Management System

• US 20080209116A1
• Filed: 05/01/2008
• Published: 08/28/2008
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Dataram Corporation (Leading Testing Laboratories, Inc.)
• Inventors: Caulkins, Jason
• Granted Patent: US 7,882,320 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Claims

1. A data storage device comprising:

a host controller interface;

a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto;

a plurality of memory device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units; and

a dataflow controller accessible to the host controller interface for managing access to the device configurations.

2. The data storage device of claim 1 wherein the device configurations bused to ones or multiples of the microprocessor units comprise individual Flash channels selectable for service from the dataflow controller.

3. The data storage device of claim 2 wherein the Flash device configuration of each selectable Flash channel comprises multiple Flash chips connected in parallel.

4. The data storage device of claim 2 wherein the Flash device configuration of each selectable Flash channel comprises multiple Flash chips connected in a daisy chain configuration.

5. The data storage device of claim 1 wherein the dataflow controller includes an onboard microprocessor with a dedicated amount of RAM.

6. The data storage device of claim 1 wherein the dataflow controller is a state machine.

7. The data storage device of claim 1 wherein the dataflow controller is hardware with a microprocessor and a dedicated portion of RAM integrated with the host controller.

8. The data storage device of claim 1 wherein the memory device configurations for each channel are of a type of NAND Flash or Phase Change Memory.

9. A Flash channel configured for data storage, comprising:

a coupled configuration of one or more Flash memory devices;

a bus structure connected to the Flash device configuration, the bus including an address line, a data line, and a control line; and

one or more microprocessor units also connected to the bus structure, and having a portion of RAM dedicated thereto.

10. The Flash channel of claim 9 wherein the Flash device configuration comprises multiple Flash chips connected in parallel to the bus structure.

11. The Flash channel of claim 9 wherein the Flash device configuration comprises multiple Flash chips connected in daisy chain to the bus structure.

12. The Flash channel of claim 9 wherein the Flash device configuration includes one or more NAND Flash devices.

13. The Flash channel of claim 9 wherein the device configuration includes one or more Phase Change Memory devices.

14. The Flash channel of claim 9 wherein, in the case of more than one microprocessor unit, a bridge is connected to the bus structure and the microprocessors are each bused to the bridge.

15. A Flash channel configured for data storage, comprising:

two or more Flash device configurations comprising one or more Flash memory devices;

two or more bus structures connected to each Flash device configuration, the bus structures each including an address line, a data line, and a control line; and

a single microprocessor unit also connected to the bus structures, the microprocessor unit having a portion of RAM dedicated thereto.