Multi-processor flash memory storage device and management system
First Claim
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1. A data storage device comprising:
- a host controller interface;
a plurality of microprocessor units each having a portion of random access volatile memory (RAM) dedicated thereto, the RAM portion having a preset threshold for valid data;
a plurality of non-volatile memory device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units;
a dataflow controller accessible to the host controller interface for managing access to the device configurations;
wherein the dataflow controller periodically compares valid data volume in the RAM portion associated with each microprocessor with the preset threshold, and upon a threshold being met or exceeded, selects and moves data that has been longest in the volatile memory portion without alteration from the RAM portion to the non-volatile memory bussed to that microprocessor, and marks locations from which the data is moved as available for writing in the volatile portion.
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Accused Products
Abstract
A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.
30 Citations
8 Claims
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1. A data storage device comprising:
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a host controller interface; a plurality of microprocessor units each having a portion of random access volatile memory (RAM) dedicated thereto, the RAM portion having a preset threshold for valid data; a plurality of non-volatile memory device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units; a dataflow controller accessible to the host controller interface for managing access to the device configurations; wherein the dataflow controller periodically compares valid data volume in the RAM portion associated with each microprocessor with the preset threshold, and upon a threshold being met or exceeded, selects and moves data that has been longest in the volatile memory portion without alteration from the RAM portion to the non-volatile memory bussed to that microprocessor, and marks locations from which the data is moved as available for writing in the volatile portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification