Efficient On-Chip Accelerator Interfaces to Reduce Software Overhead

• US 20080222383A1
• Filed: 03/09/2007
• Published: 09/11/2008
• Est. Priority Date: 03/09/2007
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Spracklen, Lawrence A., Abraham, Santosh G., Talcott, Adam R.
• Granted Patent: US 7,827,383 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/683 Invalidation

Abstract

In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Claims

1. A processor comprising:

execution circuitry configured to execute a store instruction having a data operand, wherein the execution circuitry is configured to generate a virtual address as part of executing the store instruction; and

a translation lookaside buffer (TLB) coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address.

2. The processor as recited in claim 1 wherein the TLB is configured to translate the data operand to the second physical address if the store instruction targets a hardware accelerator to which the processor is couplable.

3. The processor as recited in claim 2 wherein the store instruction targets a queue in the hardware accelerator that is configured to hold one or more commands for the hardware accelerator.

4. The processor as recited in claim 2 wherein the target is determined based on a store type corresponding to the store instruction.

5. The processor as recited in claim 4 wherein the store type is indicate by an address space identifier associated with the store instruction.

6. The processor as recited in claim 1 wherein the execution circuitry is further configured to initiate a TLB invalidation, and wherein the TLB is configured to communicate an indication of the TLB invalidation to the hardware accelerator.

7. The processor as recited in claim 6 wherein the TLB is coupled to receive an acknowledgement of the TLB invalidation from the hardware accelerator, and wherein the TLB is configured to complete the TLB invalidation responsive to receiving the acknowledgement.

8. A hardware accelerator coupled to receive an indication of a translation lookaside buffer (TLB) invalidation from a processor to which the hardware accelerator is couplable, the hardware accelerator comprising:

a physical address buffer configured to store one or more physical addresses corresponding to memory locations being accessed by the hardware accelerator; and

accelerator execution circuitry coupled to the physical address buffer and configured to perform one or more tasks assigned to the hardware accelerator, wherein the accelerator execution circuitry is configured to transmit an acknowledgement in response to the TLB invalidation indication, responsive to invalidating physical addresses in the physical address buffer that are affected by the TLB invalidation.

9. The hardware accelerator as recited in claim 8 wherein the accelerator execution circuitry is configured to abort processing of a command that reads or writes an affected page.

10. The hardware accelerator as recited in claim 8 wherein the accelerator execution circuitry is configured to delay transmission of the acknowledgement if a command is being processed that is not abortable until the command is completed.

11. The hardware accelerator as recited in claim 8 wherein the hardware accelerator is further configured to maintain a permission word indicating which thread or threads has permission to access the hardware accelerator.

12. A method comprising:

executing a store instruction having a data operand, wherein the executing comprises generating a virtual address;

translating the virtual address to a first physical address; and

selectively translating the data operand to a second physical address.

13. The method as recited in claim 12 wherein the selectively translating the data operand comprises translating the data operand to the second physical address if the store instruction targets a hardware accelerator to which the processor is couplable.

14. The method as recited in claim 13 wherein the store instruction targets a queue in the hardware accelerator that is configured to hold one or more commands for the hardware accelerator.

15. The method as recited in claim 13 further comprising determining the target of the store instruction based on a store type corresponding to the store instruction.

16. The method as recited in claim 15 wherein the store type is indicated by an address space identifier associated with the store instruction.

17. The method as recited in claim 13 further comprising initiating a TLB invalidation;

and communicating an indication of the TLB invalidation to the hardware accelerator.

18. The method as recited in claim 17 further comprising the hardware accelerator invalidating any physical page addresses affected by the TLB invalidation and stored in the hardware accelerator responsive to the indication of the TLB invalidation, and providing an acknowledgement in response to the indication.

19. The method as recited in claim 18 further comprising delaying the acknowledgement until an unabortable command completes.

20. The method as recited in claim 18 further comprising aborting a command that accesses a page affected by the TLB invalidation.

21. The method as recited in claim 17 further comprising completing the TLB invalidation responsive to receiving the acknowledgement of the TLB invalidation from the hardware accelerator.