Efficient on-chip accelerator interfaces to reduce software overhead
First Claim
1. A processor comprising:
- execution circuitry configured to execute a store instruction having one or more address operands and a data operand, wherein the execution circuitry is configured to generate a virtual address from the one or more address operands during execution of the store instruction, and wherein the execution circuitry is configured to transmit the virtual address and the data operand to a translation lookaside buffer (TLB); and
the TLB coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address responsive to the store instruction targeting a hardware accelerator, and wherein the processor is configured to transmit the first physical address and the second physical address as the address and data of a store operation to the hardware accelerator targeted by the store instruction, and wherein the processor is configured to transmit the first physical address and the data operand as the address and data of the store operation to a memory controller to access memory responsive to the store instruction targeting memory instead of the hardware accelerator.
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Accused Products
Abstract
In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.
35 Citations
18 Claims
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1. A processor comprising:
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execution circuitry configured to execute a store instruction having one or more address operands and a data operand, wherein the execution circuitry is configured to generate a virtual address from the one or more address operands during execution of the store instruction, and wherein the execution circuitry is configured to transmit the virtual address and the data operand to a translation lookaside buffer (TLB); and the TLB coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address responsive to the store instruction targeting a hardware accelerator, and wherein the processor is configured to transmit the first physical address and the second physical address as the address and data of a store operation to the hardware accelerator targeted by the store instruction, and wherein the processor is configured to transmit the first physical address and the data operand as the address and data of the store operation to a memory controller to access memory responsive to the store instruction targeting memory instead of the hardware accelerator. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A hardware accelerator coupled to receive an indication of a translation lookaside buffer (TLB) invalidation from a processor to which the hardware accelerator is couplable, the hardware accelerator comprising:
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a physical address buffer configured to store one or more physical addresses corresponding to memory locations being accessed by the hardware accelerator; and accelerator execution circuitry coupled to the physical address buffer and configured to perform one or more tasks assigned to the hardware accelerator, wherein the accelerator execution circuitry is configured to transmit an acknowledgement in response to the TLB invalidation indication, responsive to invalidating physical addresses in the physical address buffer that are affected by the TLB invalidation, and wherein the accelerator execution circuitry is configured to determine whether or not a command being processed by the accelerator execution circuitry is abortable, and wherein the accelerator execution circuitry is configured to delay transmission of the acknowledgement until the command is completed responsive to determining that the command being processed is not abortable, and wherein the accelerator execution circuitry is configured to abort processing of the command and transmit the acknowledgement without delay responsive to determining that the command is abortable. - View Dependent Claims (8, 9)
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10. A method comprising:
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executing a store instruction having one or more address operands and a data operand, wherein the executing comprises generating a virtual address from the one or more address operands; translating the virtual address to a first physical address; selectively translating the data operand to a second physical address dependent on whether or not the store instruction targets a hardware accelerator; transmitting the first physical address and the second physical address as the address and data of a store operation to the hardware accelerator responsive to determining that the store instruction targets the hardware accelerator; and transmitting the first physical address and the data operand to a memory controller responsive to determining that the store instruction targets a memory location in a memory to which the memory controller is coupled, wherein the store instruction targets the memory location instead of the hardware accelerator. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification