Methods And Circuits For Performing Margining Tests In The Presence Of A Decision Feedback Equalizer

• US 20080240219A1
• Filed: 06/06/2008
• Published: 10/02/2008
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Chen, Fred F.
• Granted Patent: US 7,596,175 B2
• Time in Patent Office: Days
• US Class Current: 375/229
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 1/241 using pseudo-errors
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Claims

1. A receiver comprising:

a. a sampler having;

i. a plurality of sampler input terminals, including at least one sampler data terminal adapted to receive an input data stream and at least one sampler reference terminal; and

ii. at least one sampler output terminal adapted to produce a sampled data stream;

b. a feedback circuit having;

i. a plurality of delay elements connected to the sampler output terminal, each delay element adapted to provide at least one historical bit from the sampled data stream; and

ii. a plurality of data-weighting circuits, each data-weighting circuit connected between one of the plurality of delay elements and at least one of the plurality of sampler input terminals and adapted to provide a weighted feedback to the sampler based on the at least one historical bit from the corresponding delay element; and

c. a multiplexer having;

i. a first multiplexer input terminal connected to the at least one sampler output terminal;

ii. a second multiplexer input terminal connected to a source of expected data; and

iii. a multiplexer output terminal connected to at least one of the sampler input terminals and adapted to provide alternatively one of the sampled data stream and the expected data.