Methods and circuits for performing margining tests in the presence of a decision feedback equalizer
First Claim
1. A receiver comprising:
- a sampler having a plurality of sampler input terminals, including at least one sampler data terminal to receive an input data stream, a sampler clock terminal to receive a clock signal, and a sampler voltage reference terminal to receive a reference voltage; and
at least one sampler output terminal;
wherein the sampler is adapted to sample the input data stream according to the clock signal and with respect to the reference voltage to produce a sampled data stream on the at least one sampler output terminal;
a multiplexer having a first multiplexer input terminal connected to the at least one sampler output terminal;
a second multiplexer input terminal connected to a source of expected data; and
a multiplexer output terminal adapted to provide alternatively one of the sampled data stream and the expected data; and
a feedback circuit having a plurality of delay elements operatively connected to the multiplexer output terminal, each delay element to provide at least one historical bit from the sampled data stream or from the expected data source from the multiplexer; and
a plurality of data-weighting circuits, each data-weighting circuit connected between one of the plurality of delay elements and at least one of the plurality of sampler input terminals and adapted to provide a weighted feedback based on the at least one historical bit from the corresponding delay element.
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Accused Products
Abstract
Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.
87 Citations
27 Claims
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1. A receiver comprising:
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a sampler having a plurality of sampler input terminals, including at least one sampler data terminal to receive an input data stream, a sampler clock terminal to receive a clock signal, and a sampler voltage reference terminal to receive a reference voltage; and
at least one sampler output terminal;
wherein the sampler is adapted to sample the input data stream according to the clock signal and with respect to the reference voltage to produce a sampled data stream on the at least one sampler output terminal;a multiplexer having a first multiplexer input terminal connected to the at least one sampler output terminal;
a second multiplexer input terminal connected to a source of expected data; and
a multiplexer output terminal adapted to provide alternatively one of the sampled data stream and the expected data; anda feedback circuit having a plurality of delay elements operatively connected to the multiplexer output terminal, each delay element to provide at least one historical bit from the sampled data stream or from the expected data source from the multiplexer; and
a plurality of data-weighting circuits, each data-weighting circuit connected between one of the plurality of delay elements and at least one of the plurality of sampler input terminals and adapted to provide a weighted feedback based on the at least one historical bit from the corresponding delay element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for establishing margins of a sampler adapted to sample a stream of input data symbols on edges of a clock signal and with respect to a reference voltage to produce a stream of data samples, the method comprising:
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creating a stream of expected symbols matching the input data symbols; calculating a weighted sum of a plurality of the expected symbols; feeding back the weighted sum of the plurality of the expected symbols to the sampler to equalize the stream of input data symbols; while feeding back the weighted sum of the plurality of expected symbols, adjusting at least one of the reference voltage or a phase of the clock signal over a plurality of values to introduce sample errors in the stream of data samples; and correlating the sample errors with the values to identify signal boundaries. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit comprising:
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a reference-voltage source to provide a reference voltage that varies over a reference-voltage range; clock circuitry to provide a clock signal over a range of clock phases; sampler having a sampler data terminal to receive an input data stream, a sampler clock terminal to receive the clock signal, and a sampler voltage reference terminal coupled to the reference-voltage source to receive the reference voltage, the sampler to sample the data stream with respect to the voltage reference on edges of the clock signal to produce a stream of data samples; an expected-data source to provide an expected data stream, the expected data stream including a plurality of historical bits; a weighting circuit coupled to the expected-data source to receive the expected data stream and to calculate a weighted sum of the plurality of historical bits; a feedback path extending from the weighting circuit to the sampler, the feedback path to apply the weighted sum to at least one of the sampler data terminal and the voltage reference terminal; and a comparison circuit to compare the stream of data samples with the expected data stream and issue error signals responsive to mismatches between the stream of data samples and the expected data stream; wherein the reference-voltage source varies the reference voltage over the reference-voltage range and the clock circuitry varies the clock signal over the range of clock phases while the comparison circuit compares the data samples with the expected data stream. - View Dependent Claims (24, 25)
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26. A receiver adapted to perform margin testing of a pulse-amplitude modulated digital input signal, comprising:
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a binary sampler having a data input terminal to receive the input signal, a reference voltage terminal to receive a reference voltage against which the input signal is measured to produce binary output values, a clock terminal to receive a clock signal that triggers sampling of the input signal according to a timing established by the clock signal, and a data output terminal to output the binary output values; an expected data source to provide a sequence of expected digital values; a comparison circuit coupled to the data output terminal and the expected data source to compare the binary output values from the sampler with the sequence of expected digital values, the comparison circuit generating an output signal responsive to the comparison; and a feedback circuit to feed back to the sampler a selective one of either the binary output values or the sequence of expected digital values; where the receiver further includes digital logic to establish a margin test mode, during which at least one of the reference voltage or the timing established by the clock signal is varied as the binary output values are compared with the sequence of expected digital values, to produce errors as a function of variation of reference voltage or sampling time. - View Dependent Claims (27)
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Specification