THIN FILM TRANSITOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20080258143A1
• Filed: 04/10/2008
• Published: 10/23/2008
• Est. Priority Date: 04/18/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Czang-Ho, CHOI, Jae-Ho, YANG, Sung-Hoon, OH, Hwa-Yeul, KIM, Sung-Ryul, CHOI, Yong-Mo, KIM, Byoung-June
• Application Number:
  US12/100,436
• Publication Number:
  US 20080258143A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

Claims

1. A method of manufacturing a thin film transistor substrate, the method comprising:

forming a first conductive pattern group including a gate electrode on a substrate;

forming a gate insulating layer on the first conductive pattern group;

forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, respectively;

forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer;

forming a protection layer including a contact hole on the second conductive pattern group; and

forming a pixel electrode electrically connected to a portion of the drain electrode through the contact hole on the protection layer.

2. The method of claim 1, wherein, in forming the second conductive pattern group, the data metal layer and the ohmic contact layer are simultaneously patterned by a wet etching.

3. The method of claim 1, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of zinc oxide.

4. The method of claim 3, wherein forming the ohmic contact layer includes adding any one of elements of group I, group III, group V, and group VII in periodic table to the zinc oxide.

5. The method of claim 1, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium oxide.

6. The method of claim 1, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium tin oxide.

7. The method of claim 1, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium zinc oxide.

8. The method of claim 1, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of an amorphous oxide semiconductor.

9. A method of manufacturing a thin film transistor substrate, the method comprising:

forming a first conductive pattern group including a gate electrode on a substrate;

sequentially depositing a gate insulating layer, an amorphous silicon layer, an oxide semiconductor layer, and a data metal layer on the first conductive pattern group;

forming a second conductive pattern group including a semiconductor layer, an ohmic contact layer, a source electrode, and a drain electrode by patterning the amorphous silicon layer, the oxide semiconductor layer, and the data metal layer, respectively;

forming a protection layer including a contact hole on the second conductive pattern group; and

forming a pixel electrode electrically connected to a portion of the drain electrode through the contact hole on the protection layer.

10. The method of claim 9, wherein, in forming the second conductive pattern group, the data metal layer and the ohmic contact layer are simultaneously patterned by a wet etching.

11. The method of claim 9, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of zinc oxide.

12. The method of claim 11, wherein forming the ohmic contact layer includes adding any one of elements of group I, group III, group V, and group VII in periodic table to the zinc oxide.

13. The method of claim 9, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium oxide.

14. The method of claim 9, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium tin oxide.

15. The method of claim 9, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of indium zinc oxide.

16. The method of claim 9, wherein forming the ohmic contact layer includes patterning the oxide semiconductor layer formed of an amorphous oxide semiconductor.

17. A thin film transistor substrate, comprising:

a gate electrode formed on a substrate;

a gate insulating layer formed to cover the gate electrode;

a semiconductor layer formed to overlap the gate electrode on the gate insulating layer;

an ohmic contact layer formed of an oxide semiconductor on the semiconductor layer; and

a source electrode and a drain electrode formed on the ohmic contact layer.

18. The thin film transistor substrate of claim 17, further comprising:

a protection layer formed on the source electrode and the drain electrode and having a contact hole; and

a pixel electrode formed on the protection layer and connected to a portion of the drain electrode through the contact hole.

19. The thin film transistor substrate of claim 17, wherein the ohmic contact layer is formed of zinc oxide.

20. The thin film transistor substrate of claim 19, wherein the ohmic contact layer includes an additive including any one of elements of group I, group III, group V, and group VII in periodic table added to the zinc oxide.

21. The thin film transistor substrate of claim 17, wherein the ohmic contact layer is formed of indium oxide.

22. The thin film transistor substrate of claim 17, wherein the ohmic contact layer is formed of indium tin oxide.

23. The thin film transistor substrate of claim 17, wherein the ohmic contact layer is formed of indium zinc oxide.

24. The thin film transistor substrate of claim 17, wherein the ohmic contact layer is formed of an amorphous oxide semiconductor.