Programmable semiconductor interposer for electronic package and method of forming

• US 20080296697A1
• Filed: 05/29/2007
• Published: 12/04/2008
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chao, Clinton, Peng, Mark Shane, Hsu, Chao-Shun
• Granted Patent: US 8,476,735 B2
• Time in Patent Office: Days
• US Class Current: 257/379
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/19011 : including integrated passive components

Abstract

Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated.

Claims

1. A semiconductor interposer comprising:

a substrate;

an array of semiconductor devices having various electrical parameters formed in said substrate;

one or more first conductive contact pads formed on a first surface of said substrate;

one or more second conductive contact pads formed on a second surface of said substrate;

one or more conductive paths passing through said substrate and connecting at least one of the first contact pads to at least one of the second contact pads;

a device selection unit formed in said substrate;

wherein said device selection unit selectively connects at least one of said devices to said first contact pads and forms a virtual element having a desired electrical parameter.

2. The interposer of claim 1 wherein said substrate comprises a silicon layer.

3. The interposer of claim 1 wherein said substrate comprises an insulating layer.

4. The interposer of claim 1 wherein said semiconductor devices comprise at least one active semiconductor device.

5. The interposer of claim 4 wherein said active semiconductor device comprise MOSFET, BJT, diode;

EDS, memory cells.

6. The interposer of claim 1 wherein said semiconductor devices comprise passive devices.

7. The interposer of claim 6 wherein said passive devices comprise resistor, capacitor, inductor, transmission line, fuse and antifuse, MEMS.

8. The interposer of claim 1 wherein said device selection unit is custom conductive layer/layers formed on said substrate.

9. The interposer of claim 1 wherein said device selection unit is an interconnect matrix formed in the top conductive layers on said structure, wherein one-time programmable fuse or antifuse is placed at each intersection of said conductive layers.

10. The interposer of claim 1 wherein said device selection unit comprises a programmable logic circuitry that may read an external instruction and configure connections between said semiconductor devices in said interposer.

11. A semiconductor interposer comprising:

a substrate;

an array of passive semiconductor devices having various electrical parameters formed in said substrate;

one or more first conductive contact pads formed on a first surface of said substrate;

one or more second conductive contact pads formed on a second surface of said substrate;

one or more conductive paths passing through said substrate and connecting at least one of the first contact pads to at least one of the second contact pads;

wherein said devices can be selectively connected to each other to form a virtual element having a desired electrical parameter and be connected to said first contact pads.

12. The interposer of claim 11 wherein said substrate comprises a silicon layer.

13. The interposer of claim 11 wherein said substrate comprises an insulating layer.

14. The interposer of claim 11 wherein said passive semiconductor devices comprise resistor, capacitor, inductor, transmission line, fuse and antifuse, MEMS.

15. The interposer of claim 11 wherein said selective connection between said devices are conducted by a device selection unit.

16. The interposer of claim 15 wherein said device selection unit is custom conductive layer/layers formed on said substrate.

17. The interposer of claim 15 wherein said device selection unit is an interconnect matrix formed in the top conductive layers on said structure, wherein one-time programmable fuse or antifuse is placed at each intersection of said conductive layers.

18. The interposer of claim 15 wherein said device selection unit comprises a programmable logic circuitry that may read an external instruction and configure connections between said semiconductor devices in said interposer.

19. An electronic package comprising:

at least one semiconductor interposer which includes a substrate, one or more first conductive contact pads formed on a first surface of said substrate, one or more second conductive contact pads formed on a second surface of said substrate, one or more conductive paths passing through said substrate and connecting at least one of the first contact pads to at least one of the second contact pads, an array of passive semiconductor devices having various electrical parameters formed in said substrate, wherein said passive semiconductor devices can be selectively connected to each other and be connected to said first contact pads and form a virtual element having a desired electrical parameter; and

at least one semiconductor integrated circuit die electrically coupled to said interposer.

20. The electronic package of claim 19 wherein said selective connection between said passive semiconductor devices are conducted by a device selection unit.