Method of manufacturing semiconductor device including trench-forming process

• US 20080305644A1
• Filed: 05/22/2008
• Published: 12/11/2008
• Est. Priority Date: 06/07/2007
• Status: Abandoned Application

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamamoto, Tsuyoshi, Noda, Yoshitaka
• Application Number:
  US12/153,634
• Publication Number:
  US 20080305644A1
• Time in Patent Office: Days
• US Class Current: 438/733
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

In a manufacturing method of a semiconductor device, a trench is formed in a semiconductor substrate by an anisotropic dry etching so as to have an aspect ratio greater than or equal to 10, and a damaged layer that is generated in a wall and a bottom of the trench due to the anisotropic dry etching is removed by an isotropic dry etching. The isotropic dry etching is performed with a first gas including carbon and fluorine and a second gas including oxygen. A temperature of the semiconductor substrate is controlled so that the damaged layer is removed from a whole surface of the wall and the bottom in the isotropic dry etching.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a trench in a semiconductor substrate by an anisotropic dry etching, wherein the trench has an aspect ratio greater than or equal to 10 and the semiconductor substrate includes silicon; and

removing a damaged layer that is generated in a wall and a bottom of the trench due to the anisotropic dry etching by an isotropic dry etching, wherein the isotropic dry etching is performed with a first gas including carbon and fluorine and a second gas including oxygen, and a temperature of the semiconductor substrate is controlled so that the damaged layer is removed from a whole surface of the wall and the bottom.

2. The method according to claim 1, wherein

the temperature of the semiconductor substrate is set to be in a range from 90°

C. to 110°

C. in the isotropic dry etching.

3. The method according to claim 2, wherein

the trench is formed by the anisotropic dry etching so as to have a vertical shape in which a width of the trench is substantially uniform in a depth direction of the trench.

4. The method according to claim 2, wherein

the trench is formed by the anisotropic dry etching so as to have a taper shape in which a width of the trench decreases toward a bottom portion of the trench.

5. The method according to claim 2, wherein

the trench is formed by the anisotropic dry etching so as to have an inverted taper shape in which a width of the trench decreases toward an opening portion of the trench.

6. The method according to claim 1, wherein

the temperature of the semiconductor substrate is set to be in a range from 20°

C. to 90°

C. in the isotropic dry etching.

7. The method according to claim 6, wherein:

the trench is formed by the anisotropic dry etching so as to have a taper shape in which a width of the trench decreases toward a bottom portion of the trench; and

the trench is etched by the isotropic dry etching so as to have a vertical shape in which the width of the trench is substantially uniform in a depth direction of the trench.

8. The method according to claim 6, wherein:

the trench is formed by the anisotropic dry etching so as to have a taper shape in which a width of the trench decreases toward a bottom portion of the trench; and

the trench is etched by the isotropic dry etching so as to have an inverted taper shape in which the width of the trench decreases toward an opening portion of the trench.

9. The method according to claim 6, wherein:

the trench is formed by the anisotropic dry etching so as to have a vertical shape in which a width of the trench is substantially uniform in a depth direction of the trench; and

the trench is etched by the isotropic dry etching so as to have an inverted taper shape in which the width of the trench decreases toward an opening portion of the trench.

10. The method according to claim 1, wherein:

the temperature of the semiconductor substrate is set to be in a range from 110°

C. to 200°

C. in the isotropic dry etching.

11. The method according to claim 10, wherein:

the trench is formed by the anisotropic dry etching so as to have an inverted taper shape in which a width of the trench decreases toward an opening portion of the trench; and

the trench is etched by the isotropic dry etching so as to have a vertical shape in which the width of the trench is substantially uniform in a depth direction of the trench.

12. The method according to claim 10, wherein:

the trench is formed by the anisotropic dry etching so as to have an inverted taper shape in which a width of the trench decreases toward an opening portion of the trench; and

the trench is etched by the isotropic dry etching so as to have a taper shape in which the width of the trench decreases toward a bottom portion of the trench.

13. The method according to claim 10, wherein:

the trench is formed by the anisotropic dry etching so as to have a vertical shape in which a width of the trench is substantially uniform in a depth direction of the trench; and

the trench is etched by the isotropic dry etching so as to have a taper shape in which the width of the trench decreases toward a bottom portion of the trench.

14. The method according to claim 1, wherein:

the temperature of the semiconductor substrate is changed between at least two temperatures that are selected from a first temperature in a range from 20°

C. to 90°

C., a second temperature in a range from 90°

C. to 110°

C., and a third temperature in a range from 110°

C. to 200°

C. during the isotropic dry etching is performed.