NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME

• US 20090003057A1
• Filed: 06/24/2008
• Published: 01/01/2009
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seungjae, Chae, Donghyuk, Kang, Dong Gu
• Granted Patent: US 7,936,601 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

Abstract

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

Claims

1. A method of operating a multi-level non-volatile memory device comprising:

accessing data, stored in the device, that is associated with read voltages; and

modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device.

2. The method according to claim 1 wherein modifying comprises:

modifying the read voltages applied to the plurality of multi-level non-volatile memory cells in response to subsequent read operations to the multi-level non-volatile memory device received after the read operation.

3. The method according to claim 1 wherein modifying comprises:

modifying the read voltages applied to the plurality of multi-level non-volatile memory cells in response to each read operation to the multi-level non-volatile memory device.

4. The method according to claim 1 wherein modifying comprises:

applying a range of preliminary read voltages to a word line, associated with the cells, between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state;

determining which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states; and

applying the read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the read command.

5. The method according to claim 4 wherein determining further comprises:

selecting the read voltage to be between two of the preliminary read voltages.

6. The method according to claim 4 further comprising:

storing the read voltage for subsequent use in accessing the cells.

7. The method according to claim 4 wherein the read operation comprises a first read operation, the minimum number comprises a first minimum number, the read voltage comprises a first read voltage, the method further comprising:

receiving a second read operation, subsequent to the first read operation, to read data from the plurality of multi-level non-volatile memory cells associated with the word line;

applying the range of preliminary read voltages to the word line between the upper read voltage limit and the lower read voltage limit;

determining which of the preliminary read voltages activated a second minimum number of the plurality of multi-level non-volatile memory cells to provide a second read voltage to discriminate between the first and second states; and

applying the second read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the second read operation.

8. The method according to claim 4 wherein applying a range of preliminary read voltages to a word line further comprises:

incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage;

reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the incremented preliminary read voltage to provide first read data;

incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage;

reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the second incremented preliminary read voltage to provide second read data; and

detecting toggling of bits between the first and second data to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.

9. The method of claim 4 further comprising:

repeatedly incrementing the preliminary read voltage until reaching the lower read voltage limit;

reading the plurality of multi-level non-volatile memory cells for each of the preliminary read voltages provided by the repeatedly incrementing; and

determining which reading of the cells, associated with the repeatedly incremented preliminary read voltages, activated a minimum number of the cells to provide the read voltage to discriminate between the first and second states.

10. The method according to claim 4 wherein applying a range of preliminary read voltages to a word line further comprises:

incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage;

accessing the plurality of multi-level non-volatile memory cells using the first incremented preliminary read voltage;

determining which of the plurality of multi-level non-volatile memory cells are not activated as having a threshold value greater than the first incremented preliminary read voltage to provide off multi-level non-volatile memory cells;

incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage;

reading the off multi-level non-volatile memory cells by applying the second incremented preliminary read voltage to the word line; and

determining a number of the off multi-level non-volatile memory cells that switch on in response to application of the second incremented preliminary read thereto to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.

11. A method of operating a multi-level non-volatile memory device comprising:

receiving a read operation to read data from a plurality of multi-level non-volatile memory cells associated with a word line;

applying a range of preliminary read voltages to the word line between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state;

determining which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states; and

applying the read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the read operation.

12. The method according to claim 11 wherein determining further comprises:

selecting the read voltage to be between two of the preliminary read voltages.

13. The method according to claim 11 further comprising:

storing the read voltage for subsequent use in accessing the cells.

14. The method of claim 11 further comprising:

repeatedly incrementing the preliminary read voltage until reaching the lower read voltage limit;

reading the plurality of multi-level non-volatile memory cells for each of the preliminary read voltages provided by the repeatedly incrementing; and

determining which reading of the cells, associated with the repeatedly incremented preliminary read voltages, activated a minimum number of the cells to provide the read voltage to discriminate between the first and second states.

15. The method according to claim 11 wherein the read operation comprises a first read operation, the minimum number comprises a first minimum number, the read voltage comprises a first read voltage, the method further comprising:

receiving a second read operation, subsequent to the first read operation, to read data from the plurality of multi-level non-volatile memory cells associated with the word line;

applying the range of preliminary read voltages to the word line between the upper read voltage limit and the lower read voltage limit;

determining which of the preliminary read voltages activated a second minimum number of the plurality of multi-level non-volatile memory cells to provide a second read voltage to discriminate between the first and second states; and

applying the second read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the second read operation.

16. The method according to claim 11 wherein applying a range of preliminary read voltages to a word line further comprises:

incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage;

reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the incremented preliminary read voltage to provide first read data;

incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage;

reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the second incremented preliminary read voltage to provide second read data; and

detecting toggling of bits between the first and second data to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.

17. The method according to claim 11 wherein applying a range of preliminary read voltages to a word line further comprises:

incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage;

accessing the plurality of multi-level non-volatile memory cells using the first incremented preliminary read voltage;

determining which of the plurality of multi-level non-volatile memory cells are not activated as having a threshold value greater than the first incremented preliminary read voltage to provide off multi-level non-volatile memory cells;

incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage;

reading the off multi-level non-volatile memory cells by applying the second incremented preliminary read voltage to the word line; and

determining a number of the off multi-level non-volatile memory cells that switch on in response to application of the second incremented preliminary read thereto to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.

18. A non-volatile memory device comprising:

an array of multi-level non-volatile memory cells associated with respective word lines;

a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation;

a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation;

a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and

a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device.

19. The non-volatile memory device according to claim 18 wherein the read voltage adjustment circuit is further configured to read data from the addressed cells using an addressed word line and configured to apply a range of preliminary read voltages to the word line between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state and configured to determine which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states;

and

wherein the high voltage generator circuit is further configured to apply the read voltage to the addressed word line to read the plurality of multi-level non-volatile memory cells to execute the read operation.

20. The non-volatile memory device according to claim 19 wherein the read voltage adjustment circuit is further configured to select the read voltage to be between two of the preliminary read voltages.

21. The non-volatile memory device according to claim 19 wherein the high voltage generator circuit is further configured to store the read voltage for subsequent use in accessing the cells.

22. An electronic system comprising:

a processor configured to coordinate operations of an electronic system;

a volatile memory, electrically coupled to the processor, configured to store and retrieve data responsive processor operations;

a system interface, electrically coupled to the processor, configured to provide communications between the processor and external systems; and

a non-volatile memory, electrically coupled to the processor, including at least one non-volatile memory device comprising;

an array of multi-level non-volatile memory cells associated with respective word lines;

a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation;

a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation;

a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and

a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device.

23. A memory card comprising:

a non-volatile memory controller configured to coordinate operations of the memory card; and

a non-volatile memory, electrically coupled to the non-volatile memory controller, comprising;

an array of multi-level non-volatile memory cells associated with respective word lines;

a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation;

a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation;

a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and

a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device.