MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
First Claim
1. A circuit device comprising:
- a word line driver having a first input to receive a first predecode value, a second input to receive a second predecode value, and an output coupled to a word line of a memory, the word line driver comprising;
a first transistor having a gate electrode coupled to the first input, a first current electrode coupled to the second input, and a second current electrode coupled to a first node;
a second transistor having a gate electrode coupled to a first voltage reference, a first current electrode coupled to a second voltage reference, and a second current electrode coupled to the first node;
a third transistor having a gate electrode coupled to the first node, a first current electrode coupled to a third voltage reference, and a second current electrode coupled to a second node;
a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node, and a second current electrode coupled to the first voltage reference; and
wherein the second node is coupled to a word line of a memory.
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Abstract
A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
16 Citations
13 Claims
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1. A circuit device comprising:
a word line driver having a first input to receive a first predecode value, a second input to receive a second predecode value, and an output coupled to a word line of a memory, the word line driver comprising; a first transistor having a gate electrode coupled to the first input, a first current electrode coupled to the second input, and a second current electrode coupled to a first node; a second transistor having a gate electrode coupled to a first voltage reference, a first current electrode coupled to a second voltage reference, and a second current electrode coupled to the first node; a third transistor having a gate electrode coupled to the first node, a first current electrode coupled to a third voltage reference, and a second current electrode coupled to a second node; a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node, and a second current electrode coupled to the first voltage reference; and wherein the second node is coupled to a word line of a memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory comprising:
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a plurality of global word lines; global word line driver circuitry having a plurality of outputs, each output coupled to a corresponding global word line of the plurality of global word lines; address decode circuitry having an output to provide a predecode value; a local bit cell array comprising a plurality of local word lines; local word line driver circuitry having an input coupled to the output of the address decode circuitry, an input coupled to corresponding global word line of the plurality of global word lines, and a plurality of outputs, each output coupled to a corresponding local word line of the plurality of local word lines, wherein the local word line driver circuitry comprises a plurality of voltage level shifters, each voltage level shifter associated with a corresponding local word line of the local bit cell array; wherein the global word line driver circuitry and address decode circuitry are operable in a first voltage domain; and wherein the local bit cell array and local word line driver circuitry are operable in a second voltage domain different than the first voltage domain. - View Dependent Claims (10, 11, 12, 13)
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Specification