METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS

• US 20090055789A1
• Filed: 09/18/2008
• Published: 02/26/2009
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: Lisa G. Mcilrath
• Original Assignee: Lisa G. Mcilrath
• Inventors: McIlrath, Lisa G.
• Granted Patent: US 8,032,857 B2
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Claims

1. A method for layout for a 3-D integrated circuit, the method comprising the steps of:

identifying a dimensionality of a cell; and

selecting a circuit level for a 3-D cell.

2. The method of claim 1 further comprising the step of:

providing an instantiation of a 2-D child cell within the 3-D cell.

3. The method of claim 1 wherein the steps are performed via a graphical user interface in a computer system.

4. The method of claim 1 further comprising the step of:

providing an instantiation of a 2-D circuit level projection of a 3-D cell within a 2-D cell.

5. The method of claim 2 wherein the steps are performed via a graphical user interface in a computer system.

6. A user interface comprising:

a component capable of enabling input of a cell name for a cell; and

a component capable of selecting a technology for said cell.

7. A computer readable medium having computer executable code embodied therein, said computer executable code being capable of causing a computer to implement the user interface of claim 6.

8. A user interface for providing information for a layout of a 3-D integrated circuit, the user interface comprising:

a component capable of selecting a circuit level for a 3-D cell.

9. A computer readable medium having computer executable code embodied therein, said computer executable code being capable of causing a computer to implement the user interface of claim 8.

10. A user interface comprising:

a component capable of enabling input of a cell name for a child cell; and

a component capable of selecting a circuit level for said child cell.

11. The user interface of claim 10 wherein said child cell is a 2-D child cell;

and wherein said 2-D child cell is a 2-D circuit level projection of a 3-D cell.

12. A system for layout for a 3-D integrated circuit, the system comprising:

at least one processor;

a display device;

at least one computer usable medium having computer readable code embodied there in, said computer readable code being capable of causing said at least one processor to;

provide a user interface comprising;

a component capable of enabling input of a cell name for a cell; and

a component capable of selecting a technology for said cell;

a component capable of selecting a circuit level for a 3-D cell; and

a component capable of enabling input of a cell name for a child cell; and

a component capable of selecting a circuit level for said child cell.