Methods and systems for computer aided design of 3D integrated circuits

• US 8,032,857 B2
• Filed: 09/18/2008
• Issued: 10/04/2011
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: R3 Logic, Inc.
• Original Assignee: R3 Logic, Inc.
• Inventors: McIlrath, Lisa G.
• Primary Examiner(s): Doan; Nghia
• Application Number:
  US12/233,260
• Publication Number:
  US 20090055789A1
• Time in Patent Office: 1,111 Days
• Field of Search: 716/54, 716/55, 716100-104, 716/106, 716/107, 716110-111, 716118-119, 716/132, 716/135, 716/139, 716/126
• US Class Current: 716/139
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Claims

1. A system for computer aided design of a 3-D integrated circuit, the system comprising:

a computer having at least one processor;

a hierarchical cell data structure defined on said computer;

a 3-D hierarchical cell comprising a part of said hierarchical cell data structure and representing said 3-D integrated circuit; and

a graphical user interface in communication with said at least one processor, said graphical user interface configured to define said 3-D hierarchical cell, said graphical user interface having,

a cell name input component configured to input a name for said 3-D hierarchical cell of said 3-D integrated circuit;

a technology selection component for said 3-D hierarchical cell;

a 3-D technology file referenced by said technology selection component and containing information relating to how said 3-D integrated circuit is to be constructed said 3-D technology file providing means to define rules for electrical or physical interaction between geometries for 3-D design layers on specific circuit levels;

a circuit level selection component configured to specify a 2-D fabrication technology for said 3-D integrated circuit; and

a child cell name input component for a child cell of said 3-D hierarchical cell.

2. The system of claim 1, wherein said 3-D technology file identifies a layer of said 3-D integrated circuit with a particular physical location in said 3-D integrated circuit.

3. The system of claim 1, wherein said 3-D technology file defines a geometric constraint for a material layer of said 3-D integrated circuit.

4. The system of claim 1, wherein said graphical user interface has a drawing layer palette component for said 3-D hierarchical cell.

5. The system of claim 1, wherein said 3-D technology file identifies a bond layer located between two selected circuit levels.

6. The system of claim 1, wherein said hierarchical cell data structure comprises a hierarchical tree.

7. A method of designing a 3-D integrated circuit comprising:

displaying an interactive menu on a graphical user interface;

receiving a user input to define a 3-D hierarchical layout cell, said 3-D hierarchical layout cell comprising a 3-D child cell and a 2-D child cell;

providing, on said interactive menu, a technology selection component for said 3-D hierarchical layout cell;

referencing a 3-D technology file based on a selected technology said 3-D technology file providing means to define rules for electrical or physical interaction between geometries for 3-D design layers on specific circuit levels;

instantiating said 2-D child cell within said 3-D hierarchical layout cell;

providing, on said interactive menu, a circuit level selection component configured to specify a 2-D fabrication technology for said 3-D integrated circuit;

projecting said 3-D child cell within said 2-D child cell; and

saving said 3-D technology file containing assembly and fabrication information for said 3-D integrated circuit.

8. The method of claim 7, wherein said 3-D technology file identifies a layer of said 3-D integrated circuit with a particular physical location in said 3-D integrated circuit.

9. The method of claim 7, wherein said 3-D technology file defines a geometric constraint for a material layer of said 3-D integrated circuit.

10. The method of claim 7, wherein said 3-D technology file defines a bond layer located between two selected circuit levels.

11. The method of claim 7, further comprising the step of providing, on said graphical user interface, a drawing-layer palette for said 3-D hierarchical layout cell.

12. The method of claim 7, wherein said 3-D hierarchical layout cell further comprises a hierarchical tree.

13. A method for computer aided design of a 3-D integrated circuit, the system comprising:

providing a computer having at least one processor;

defining a hierarchical cell data structure on said computer;

defining a 3-D hierarchical cell representing said 3-D integrated circuit;

using a graphical user interface in communication with said at least one processor to define said 3-D hierarchical cell;

providing a cell name via said graphical user interface to name said 3-D hierarchical cell of said 3-D integrated circuit;

configuring, via said graphical user interface, a 3-D technology file containing information relating to how said 3-D integrated circuit is to be constructed said 3-D technology file providing means to define rules for electrical or physical interaction between geometries for 3-D design layers on specific circuit levels;

specifying, via said graphical user interface, a 2-D fabrication technology for said 3-D integrated circuit; and

providing a child cell name, via said graphical user interface, naming a child cell of said 3-D hierarchical cell.