BATTERY CHARGER

• US 20090102432A1
• Filed: 12/28/2007
• Published: 04/23/2009
• Est. Priority Date: 10/19/2007
• Status: Abandoned Application

• Current Assignee: Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hon Hai Precision Industry Co., Ltd.
• Inventors: CHAO, KUO-SHENG, HSIEH, MING-CHIH
• Application Number:
  US11/965,751
• Publication Number:
  US 20090102432A1
• Time in Patent Office: Days
• US Class Current: 320/163
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence

Abstract

An exemplary battery charger includes an input interface arranged to connect to a DC power source, having a positive terminal and a negative terminal; an output interface arranged to connect to a battery, having a positive terminal and a negative terminal; a switch circuit connected between the positive terminals of the input interface and the output interface, comprising a control terminal; a detecting resistor connected between the negative terminals of the input interface and the output interface; a detecting circuit connected between the negative terminals of the input interface and the output interface to detect a voltage across the detecting resistor and output a digital signal; and a processor receiving the voltage signal to determine whether the battery is fully charged and generate a voltage signal to the control terminal of the switch circuit via an inverting circuit for turning off the switch circuit when the battery is fully charged.

Claims

1. A battery charger comprising:

an input interface arranged to connect to a DC power source, having a positive terminal and a negative terminal;

an output interface arranged to connect to a battery, having a positive terminal and a negative terminal;

a switch circuit connected between the positive terminals of the input interface and the output interface, comprising a control terminal;

a detecting resistor connected between the negative terminals of the input interface and the output interface;

a detecting circuit connected between the negative terminals of the input interface and the output interface to detect a voltage across the detecting resistor and output digital signals; and

a processor receiving a first digital signal from the detecting circuit upon the condition that the switch circuit is off, receiving a second digital signal from the detecting circuit upon the condition that the switch circuit is on, subtracting the first digital signal from the second digital signal to get a third digital signal, comparing the third digital signal with a reference value to determine if the battery is fully charged, and generating a voltage signal to the control terminal of the switch circuit via an inverting circuit for turning off the switch circuit when the battery is fully charged.

2. The battery charger as claimed in claim 1, wherein the switch circuit comprises a first NMOS transistor and a second NMOS transistor, the drain of the first NMOS transistor is connected to the positive terminal of the input interface, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the. positive terminal of the output interface, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and together serve as the control terminal of the switch circuit to connect the inverting circuit.

3. The battery charger as claimed in claim 1, wherein the inverting circuit comprises a third NMOS transistor, a diode, and a third resistor, the drain of the third NMOS transistor is connected to a power source via the third resistor, the source of the NMOS transistor is connected to the anode of the diode, and the cathode of the diode is connected to the negative terminal of the input interface, the gate of the third NMOS transistor is connected to the processor to receive the voltage signal, and the drain of the third NMOS transistor is connected to the control terminal of the switch circuit to control the switch circuit to turn on and off according to the voltage signal.

4. The battery charger as claimed in claim 1, wherein the detecting circuit comprises a first resistor, a second resistor, a comparator, a capacitor, and an A/D converter, an inverting terminal of the comparator is connected to the negative terminal of the input interface via the first resistor, the second transistor and the capacitor are connected in parallel between the inverting terminal and an output terminal of the comparator, a non-inverting terminal of the comparator is connected to the negative terminal of the output interface, the output terminal of the comparator is connected to the processor via the A/D converter for transmitting the digital signal according to a voltage on the detecting resistor.

6. The battery charger as claimed in claim 4, wherein the reference value is equal to a voltage generated by the comparator when the battery is fully charged.

5. (canceled)

7. A compensating method in using a battery charger, the compensating method comprising:

providing an input interface with a positive terminal and a negative terminal;

an output interface with a positive terminal and a negative terminal;

a switch circuit connected between the positive terminals of the input interface and the output interface;

a detecting resistor connected between the negative terminals of the input interface and the output interface;

a detecting circuit connected between the negative terminals of the input interface and the output interface;

a processor connected to the detecting circuit, wherein a reference value is stored in the processor; and

an inverting circuit connected between the processor and the switch circuit;

connecting a DC power source to the input interface;

connecting a battery to the output interface;

detecting a first digital value between the negative terminals of the input interface and the output interface by the detecting circuit upon the condition that the switch circuit is off, and sending the first digital value to the processor;

detecting a second digital value between the negative terminals of the input interface and the output interface by the detecting circuit upon the condition that the switch circuit is on, and sending the second digital value to the processor;

subtracting the first digital value from the second digital value to get a third digital value by the processor;

comparing the third digital value with the reference value by the processor;

turning off the switch circuit via the inverting circuit by the processor upon the condition that the third digital value is less than the reference value; and

turning on the switch circuit via the inverting circuit by the processor upon the condition that the third digital value is more than or equal to the reference value.

8. The compensating method as claimed in claim 7, wherein the switch circuit comprises a first NMOS transistor and a second NMOS transistor, the drain of the first NMOS transistor is connected to the positive terminal of the input interface, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the positive terminal of the output interface, the gates of the first and second NMOS transistors are connected to the inverting circuit.

9. The compensating method as claimed in claim 7, wherein the inverting circuit comprises a third NMOS transistor, a diode, and a third resistor, the drain of the third NMOS transistor is connected to a power source via the third resistor, the source of the NMOS transistor is connected to the anode of the diode, and the cathode of the diode is connected to the negative terminal of the input interface, the gate of the third NMOS transistor is connected to the processor, and the drain of the third NMOS transistor is connected to the switch circuit to control the switch to turn on and off according to the processor.

10. The compensating method as claimed in claim 7, wherein the detecting circuit comprises a first resistor, a second resistor, a comparator, a capacitor, and an A/D converter, an inverting terminal of the comparator is connected to the negative terminal of the input interface via the first resistor, the second transistor and the capacitor are connected in parallel between the inverting terminal and an output terminal of the comparator, a non-inverting terminal of the comparator is connected to the negative terminal of the output interface, the output terminal of the comparator is connected to the processor via the A/D converter for transmitting digital signals according to a voltage on the detecting resistor.

11. The compensating method as claimed in claim 10, wherein the reference value is equal to a voltage generated by the comparator when the battery is fully charged.