METHOD AND SYSTEM FOR REDUCING THE IMPACT OF LATENCY ON VIDEO PROCESSING

• US 20090110051A1
• Filed: 10/29/2007
• Published: 04/30/2009
• Est. Priority Date: 10/29/2007
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Kendall, Chad, Sankar, Narendra, Lindsay, Steven B.
• Application Number:
  US11/927,050
• Publication Number:
  US 20090110051A1
• Time in Patent Office: Days
• US Class Current: 375/240.10
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

The disclosed systems and methods relate to reducing the effect of video processing latency in devices that utilize PCI Express Active State Power Management (PCI-E ASPM). Power state transition delay may be reduced by initiating an early L1 exit based on a video processing stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may be embodied in a video processing device that uses a video accelerator with a PCI-E interface.

Claims

1. A method for reducing the impact of latency on video processing, wherein the method comprises:

entering a low power PCI-E state;

determining a memory access time according to a video processing event; and

transitioning to a full power PCI-E state based on the memory access time.

2. The method in claim 1, wherein the video processing event is encoding a video frame.

3. The method in claim 2, wherein the encoded video frame is multiplexed with an audio frame.

4. The method in claim 1, wherein the video processing event is decoding a video frame.

5. The method in claim 4, wherein the decoded video frame is post-processed.

6. The method in claim 1, wherein transitioning to the full power state occurs after a delay.

7. The method in claim 6, wherein the delay is based on time.

8. The method in claim 1, wherein the video processing event is receiving a video signal.

9. The method in claim 8, wherein the video signal is an analog video signal.

10. The method in claim 9, wherein an early low power exit indication is generated according to a vertical sync input.

11. The method in claim 8, wherein the video signal is a digital video signal.

12. The method in claim 11, wherein an early low power exit indication is generated according to a first arrival of data.

13. A system for reducing the impact of latency during video processing, wherein the system comprises:

an interface having a power management feature, wherein the power management feature comprises a low power PCI-E state and a full power PCI-E state; and

a video processor for instructing the interface to initiate a transition from the low power PCI-E state to the full power PCI-E state, wherein the video processor determines a requirement for the full power PCI-E state.

14. The system in claim 13, wherein the video processor comprises an encoder.

15. The system in claim 13, wherein the controller comprises a decoder.

16. The system in claim 13, wherein the controller generates a delay between the determination of the full power PCI-E state requirement and the initiation of the transition.

17. The system in claim 16, wherein the delay is based on time.

18. A video processor, wherein the video processor comprises:

a video encoder for compressing video data and instructing a PCI-E interface to initiate a transition from a low power state to a full power state; and

a multiplexer for merging the compressed video data with a digital audio signal.

19. The video processor of claim 18, wherein the transition of the PCI-E interface is initiated before the compressed video data is merged with the digital audio signal.

20. A video processor, wherein the video processor comprises:

a video decoder for decompressing video data and instructing a PCI-E interface to initiate a transition from a low power state to a full power state; and

a post-processor for formatting the decompressing video data.

21. The video processor of claim 20, wherein the transition of the PCI-E interface is initiated before the decompressed video data is formatted.

22. A video processor, wherein the video processor comprises:

a video transcoder for changing the compression scheme of encoded video data from a first standard to a second standard and instructing a PCI-E interface to initiate a transition from a low power state to a full power state.

23. The video processor of claim 22, wherein the transcoder initiates the PCI-E interface transition after the encoded video data is decompressed according to the first standard.