METHOD FOR INTEGRATING NVM CIRCUITRY WITH LOGIC CIRCUITRY

• US 20090111226A1
• Filed: 10/29/2007
• Published: 04/30/2009
• Est. Priority Date: 10/29/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar L.
• Granted Patent: US 7,745,344 B2
• Time in Patent Office: Days
• US Class Current: 438/258
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.

Claims

1. A method comprising:

providing a substrate having a first defined area and a second defined area that is electrically separated from first defined area;

providing a first layer of gate material overlying the substrate in both the first defined area and the second defined area;

providing multiple adjoining sacrificial layers overlying the first layer of gate material;

using the multiple adjoining sacrificial layers to form transistor control electrodes in the first defined area wherein at least one of the adjoining sacrificial layers is not completely removed;

using at least one of the adjoining sacrificial layers to pattern a transistor control electrode in the second defined area; and

completing formation of transistors in both the first defined area and the second defined area.

2. The method of claim 1 wherein the at least one of the adjoining sacrificial layers is immediately adjacent the transistor control electrode in the second defined area.

3. The method of claim 1 wherein the multiple adjoining sacrificial layers further comprises a first nitride layer overlying an oxide layer that overlies a second nitride layer.

4. The method of claim 1 wherein the first defined area comprises a non-volatile memory area for implementing non-volatile memory cells and the second defined area comprises a logic area for implementing transistors that implement logic functions.

5. The method of claim 1 wherein the first defined area is electrically isolated from the second defined area by an amount corresponding to a minimum photolithography limit.

6. The method of claim 1 wherein at least one of the multiple adjoining sacrificial layers comprises a polishing stop layer for use in chemical mechanical polishing, at least one of the multiple adjoining sacrificial layers comprises an etch stop layer for use in chemical etching, and at least one of the multiple adjoining sacrificial layers comprises an anti-reflective coating (ARC) layer.

7. The method of claim 1 wherein the multiple adjoining sacrificial layers are completely removed at completion of processing of the first defined area and the second defined area and further comprises:

an anti-reflective coating (ARC) layer overlying the substrate;

an oxide layer overlying the anti-reflective coating layer; and

a nitride layer overlying the oxide layer.

8. A method of forming an integrated circuit comprising a first region and a second region formed over a substrate and separated by an isolation region, the method comprising:

forming a first gate electrode material layer overlying the substrate in both the first region and the second region;

forming a plurality of sacrificial layers overlying the first gate electrode material layer in both the first region and the second region prior to forming any devices in the first region and the second region;

using the plurality of sacrificial layers to form a first type of device in the first region; and

using at least one of the plurality of sacrificial layers to form a second type of device in the second region.

9. The method of claim 8 further comprising removing the plurality of sacrificial layers from the first region prior to forming gate electrodes corresponding to the second type of device in the second region.

10. The method of claim 8, wherein the at least one of the plurality of sacrificial layers used to form the second type of device is immediately adjacent to the first gate electrode material layer.

11. The method of claim 8, wherein the at least one of the plurality of sacrificial layers used to form the second type of device is an anti-reflective coating (ARC) layer.

12. The method of claim 11, wherein the ARC layer is used to pattern a gate electrode corresponding to the second type of device formed in the second region.

13. The method of claim 8, wherein the plurality of sacrificial layers comprises an anti-reflective coating (ARC) layer used to pattern a gate electrode corresponding to the second type of device formed in the second region, a polishing stop layer used to stop polishing of a polysilicon layer formed in both the first region and the second region, and an etch stop layer used to stop etching the polishing stop layer in both the first region and the second region.

14. The method of claim 8, wherein the first region is a memory region and the second region is a logic region.

15. The method of claim 14, wherein the first type of device includes a control gate and a select gate and wherein the second type of device includes only one gate.

16. A method of forming an integrated circuit comprising a memory region and a logic region formed over a substrate and separated by an isolation region, the method comprising:

forming a first gate electrode material layer overlying the substrate in both the memory region and the logic region;

forming a plurality of sacrificial layers overlying the first gate electrode material layer in both the memory region and the logic region prior to forming any devices in the memory region and the logic region;

using the plurality of sacrificial layers to form a non-volatile memory device in the memory region; and

using at least one of the plurality of sacrificial layers to form a logic device in the logic region, wherein the at least one of the plurality of sacrificial layers used to form the logic device is an anti-reflective coating (ARC) layer used to pattern a gate electrode corresponding to the logic region.

17. The method of claim 16 further comprising removing the plurality of sacrificial layers from the memory region prior to forming the gate electrode corresponding to the logic device in the logic region.

18. The method of claim 16, wherein the at least one of the plurality of sacrificial layers used to form the logic device is immediately adjacent to the first gate electrode material layer.

19. The method of claim 16, wherein the plurality of sacrificial layers comprises a polishing stop layer used to stop polishing of a polysilicon layer formed in both the memory region and the logic region, an etch stop layer used to stop etching the polishing stop layer in both the memory region and the logic region.

20. The method of claim 19, wherein the ARC layer contains nitrogen, the polishing stop layer contains nitrogen, and the etch stop layer contains oxygen.