Method for integrating NVM circuitry with logic circuitry

• US 7,745,344 B2
• Filed: 10/29/2007
• Issued: 06/29/2010
• Est. Priority Date: 10/29/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar L.
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): LAURENZI, MARK A
• Application Number:
  US11/926,348
• Publication Number:
  US 20090111226A1
• Time in Patent Office: 974 Days
• Field of Search: 257/252, 257/288, 257/314, 257/410, 438/14, 438/258, 438/700, 438/239
• US Class Current: 438/738
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.

Claims

1. A method comprising:

providing a substrate having a first defined area for formation of a non-volatile memory cell having a select gate that is laterally adjacent a control gate and having a second defined area that is electrically separated from the first defined area, the second defined area being for formation of a transistor having a gate electrode;

providing a first layer of gate material overlying the substrate in both the first defined area and the second defined area;

providing multiple adjoining planar sacrificial layers respectively containing overlying nitrogen, oxygen and nitrogen in both the first defined area and the second defined area and overlying the first layer of gate material;

using the multiple adjoining planar sacrificial layers to form the select gate and the control gate in the first defined area wherein the nitrogen underlying the oxygen of the multiple adjoining planar sacrificial layers is not completely removed and the oxygen and overlying nitrogen are removed;

after formation of the select gate and control gate, using the nitrogen layer of the adjoining planar sacrificial layers to pattern the gate electrode of the transistor in the second defined area; and

completing formation of transistors in both the first defined area and the second defined area.

2. The method of claim 1 wherein the first defined area is electrically isolated from the second defined area by an amount corresponding to a minimum photolithography limit.

3. The method of claim 1 wherein the nitrogen overlying the oxygen of the multiple adjoining planar sacrificial layers functions as a polishing stop layer for use in chemical mechanical polishing, the oxygen of the multiple adjoining planar sacrificial layers functions as an etch stop layer for use in chemical etching, and the nitrogen underlying the oxygen of the multiple adjoining planar sacrificial layers functions as an anti-reflective coating (ARC) layer.

4. The method of claim 1 wherein the multiple adjoining planar sacrificial layers are completely removed at completion of processing of the first defined area and the second defined area and further comprises:

the nitrogen underlying the oxygen functioning as an anti-reflective coating (ARC) layer overlying the substrate;

the oxygen functioning as an oxide layer overlying the anti-reflective coating layer; and

the nitrogen overlying the oxygen functioning as a nitride layer overlying the oxide layer.

5. A method of forming an integrated circuit comprising a first region and a second region formed over a substrate and separated by an isolation region, the method comprising:

forming a first gate electrode material layer overlying the substrate in both the first region and the second region;

forming a plurality of planar sacrificial layers respectively comprising overlying layers of nitrogen, oxygen and nitrogen in both the first region and the second region and overlying the first gate electrode material layer in both the first region and the second region prior to forming any devices in the first region and the second region;

using the plurality of planar sacrificial layers to form a memory cell having a select gate that is laterally adjacent a control gate in the first region, wherein the layers of oxygen and overlying nitrogen of the plurality of planar sacrificial layers are removed; and

after formation of the select gate and control gate, using the nitrogen that is underlying the oxygen of the plurality of planar sacrificial layers to form a control electrode of a second type of device in the second region.

6. The method of claim 5, wherein the nitrogen underlying the oxygen is used as an anti-reflective coating (ARC) layer.

7. The method of claim 6, wherein the nitrogen underlying the oxygen functions as an anti-reflective coating (ARC) layer overlying the substrate, the oxygen functions as an oxide layer overlying the anti-reflective coating layer, and the nitrogen overlying the oxygen functions as a nitride layer overlying the oxide layer.

8. A method of forming an integrated circuit comprising a memory region and a logic region formed over a substrate and separated by an isolation region, the method comprising:

forming a first gate electrode material layer overlying the substrate in both the memory region and the logic region;

forming a plurality of planar sacrificial layers respectively containing overlying layers of nitrogen, oxygen and nitrogen and overlying the first gate electrode material layer in both the memory region and the logic region prior to forming any devices in the memory region and the logic region;

using the plurality of sacrificial layers to form a non-volatile memory device in the memory region, the non-volatile memory device having a select gate that is laterally adjacent a control gate, wherein the layers of oxygen and overlying nitrogen of the plurality of planar sacrificial layers are removed; and

using the nitrogen underlying the oxygen of the plurality of planar sacrificial layers to form a logic device in the logic region, wherein the nitrogen underlying the oxygen of the plurality of planar sacrificial layers is used to form a gate electrode of the logic device and functions as an anti-reflective coating (ARC) layer used to pattern the gate electrode.

9. The method of claim 8 further comprising removing the oxygen and the nitrogen overlying the oxygen of the plurality of planar sacrificial layers from the memory region prior to forming the gate electrode of the logic device in the logic region.

10. The method of claim 8, wherein the the oxygen functions as an oxide layer overlying the anti-reflective coating layer, and the nitrogen overlying the oxygen functions as a nitride layer overlying the oxide layer, the oxygen and the nitrogen overlying the oxygen being removed prior to formation of the gate electrode of the logic device.