Method and System for Providing a Low-Profile Semiconductor Assembly

• US 20090127703A1
• Filed: 11/20/2007
• Published: 05/21/2009
• Est. Priority Date: 11/20/2007
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Lee, Michael G.
• Application Number:
  US11/942,782
• Publication Number:
  US 20090127703A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/83007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
• CPC Class Codes: H01L 2224/8314 Guiding structures outside the body
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.

Claims

1. A semiconductor assembly, comprising:

a substrate having a first surface;

a chip coupled to the substrate, the chip having a second surface facing the first surface of the substrate, the chip spaced apart from the substrate forming a gap, wherein at least a portion of the substrate is coupled to the chip by a plurality of solder bumps;

the plurality of solder bumps comprising a deformable material, such that as a height of the gap between the chip and the substrate increases, the plurality of solder bumps are operable to deform into a stretched state;

an underfill material applied between the substrate and the chip, the underfill material operable to substantially fill the gap between the chip and the substrate and surround the plurality of solder bumps in the stretched state; and

a plurality of barricades comprising a plurality of non-conductive protrusions disposed between the first surface of the substrate and the second surface of the chip, the plurality of barricades being operable to confine the plurality of solder bumps in a compressed state.

2. The assembly of claim 1, wherein the plurality of barricades are disposed on the first surface of the substrate.

3. The assembly of claim 1, wherein the plurality of barricades are disposed on the second surface of the chip.

4. The assembly of claim 1, wherein the plurality of barricades are substantially perpendicular to the substrate.

5. The assembly of claim 1, wherein each of the plurality of barricades has a rectangular shape.

6. The assembly of claim 1, wherein the plurality of barricades are formed using photolithography.

7. The assembly of claim 1, wherein each of the plurality of barricades comprises a polymer.

8. The assembly of claim 1, wherein the underfill material comprises an epoxy.

9. The assembly of claim 1, wherein:

the substrate has a first coefficient of thermal expansion;

the chip has a second coefficient of thermal expansion; and

the first coefficient of thermal expansion is different from the second coefficient of thermal expansion.

10. The assembly of claim 1, wherein the plurality of barricades comprises at least two barricades positioned in contact with each other.

11. The assembly of claim 1, wherein each of the plurality of solder bumps comprises copper.

12. The assembly of claim 1, wherein the substrate comprises a second chip.

13. A method for providing a semiconductor assembly, comprising:

providing a substrate having a first surface;

coupling a chip to the substrate, the chip having a second surface facing the first surface of the substrate, the chip spaced apart from the substrate forming a gap, wherein at least a portion of the substrate is coupled to the chip by a plurality of solder bumps;

the plurality of solder bumps comprising a deformable material, such that as a height of the gap between the chip and the substrate increases, the plurality of solder bumps are operable to deform into a stretched state; and

applying an underfill material between the substrate and the chip, the underfill material operable to substantially fill the gap between the chip and the substrate and surround the plurality of solder bumps in the stretched state.

14. The method of claim 13, further comprising disposing a plurality of barricades comprising a plurality of non-conductive protrusions between the first surface of the substrate and the second surface of the chip, the plurality of barricades being operable to confine the plurality of solder bumps in a compressed state.

15. The method of claim 14, wherein disposing a plurality of barricades comprising a plurality of non-conductive protrusions between the first surface of the substrate and the second surface of the chip comprises disposing the plurality of barricades on the first surface of the substrate.

16. The method of claim 14, wherein disposing a plurality of barricades comprising a plurality of non-conductive protrusions between the first surface of the substrate and the second surface of the chip comprises disposing the plurality of barricades on the second surface of the chip.

17. The method of claim 14, wherein the plurality of barricades are substantially perpendicular to the substrate.

18. The method of claim 14, wherein each of the plurality of barricades has a rectangular shape.

19. The method of claim 14, wherein the plurality of barricades are formed using photolithography.

20. The method of claim 14, wherein each of the plurality of barricades comprises a polymer.

21. The method of claim 14, wherein the plurality of barricades comprises at least two barricades positioned in contact with each other.

22. The method of claim 13, wherein the underfill material comprises an epoxy.

23. The method of claim 13, wherein:

the substrate has a first coefficient of thermal expansion;

the chip has a second coefficient of thermal expansion; and

the first coefficient of thermal expansion is different from the second coefficient of thermal expansion.

24. The method of claim 13, wherein each of the plurality of solder bumps comprises copper.

25. The method of claim 13, wherein the substrate comprises a second chip.