CACHE MANAGEMENT DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS

• US 20090198897A1
• Filed: 02/01/2008
• Published: 08/06/2009
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blackmore, Robert S., Xue, Hanhong, Arimilli, Ravi K., Kim, Chulho, Sinharoy, Balaram
• Granted Patent: US 8,327,101 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.

Claims

1. A data processing system comprising:

a processor;

a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data;

at least one lower level cache that buffers data from memory for utilization during processor execution;

processing logic for completing an asynchronous memory move (AMM) operation, wherein;

the processor receives an AMM ST instruction and processes an effective address move of data from a first effective address to a second effective address; and

asynchronous memory mover logic then completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions.

2. The data processing system of claim 1, further comprising:

processing logic for checking a status/control field of the AMM ST instruction for an indication of a requested treatment of the at least one lower level cache on completion of the AMM operation;

in response to the status/control field indicating an update to the at least one cache should be performed;

logic for automatically forwarding a copy of the data from the data move to the at least one lower level cache; and

logic for triggering an update of a coherency state for a cache line within the at least one lower level cache in which the copy of the data is placed.

3. The data processing system of claim 2, wherein the asynchronous memory mover logic is a part of a asynchronous memory mover that contains registers for storing parameters of the AMM ST instruction that enable completion of the AMM operation, and said logic for triggering the update includes logic for retrieving the coherency status from a coherency state register associated with the parameters of the AMM ST instruction, stored within the registers of the asynchronous memory mover.

4. The data processing system of claim 1, wherein the logic for forwarding the data includes logic for forwarding the data from the source real address and tagging the data with the destination effective address corresponding to the destination real address.

5. The data processing system of claim 1, wherein the logic for forwarding the data includes:

logic for evaluating a size of the data being moved relative to a size of the at least one lower level cache; and

logic for forwarding only a first subset of the data to the at least one lower level cache when the size of the data exceeds a threshold size which would overrun the lower level cache.

6. The data processing system of claim 5, wherein:

the at least one lower level cache includes an L2 cache and an L3 cache; and

said logic for forwarding only a first subset of the data comprises;

logic for forwarding one or more L2 cache line sized data to the L2 cache from the first portion of the data being moved;

logic for forwarding one or more L3 cache line sized data to the L3 cache from a sequentially following second portion of data being moved; and

logic for forwarding remaining data to the memory;

wherein not all data being moved are placed within the L2 and L3 cache and wherein the L2 and L3 caches are not filled with data from the data move operation.

7. The data processing system of claim 1, wherein said processing logic further comprises:

logic for determining when the destination effective address of the AMM ST instruction is and effective address that is represented within the lower level cache; and

logic for responding to the addresses being the same by performing one of;

triggering an automatic update of the data within the lower level cache within cache lines addressed with the corresponding effective address; and

triggering an update of the cache state for the cache lines to an invalid (I) state, to force the cache to load coherent data from the memory when the data associated with the effective address is requested by the processor.

8. In a data processing system having a processor, a memory subsystem including a memory and at least one lower level cache, a method comprising:

completing a move of data in virtual address space, in response to receiving an AMM ST instruction, wherein the move includes a processor-level move of data from a first effective address to a second effective address, and

completing an asynchronous memory move (AMM) operation generated by the AMM ST instruction, wherein the AMM operation completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions;

performing an update to the at least one lower level cache based on the completion of the physical move.

9. The method of claim 8, wherein the performing an update further comprises:

checking a status/control field of the AMM ST instruction for an indication of a requested treatment of the at least one lower level cache on completion of the AMM operation;

in response to the status/control field indicating an update to the at least one cache should be performed;

automatically forwarding a copy of the data from the physical move to the at least one lower level cache; and

triggering an update of a coherency state for a cache line within the at least one lower level cache in which the copy of the data is placed.

10. The method of claim 9, wherein the asynchronous memory mover contains registers for storing parameters of the AMM ST instruction that enable completion of the AMM operation, and said triggering the update further comprises retrieving the coherency status from a coherency state register associated with the parameters of the AMM ST instruction, stored within the registers of the asynchronous memory mover.

11. The method of claim 8, wherein the performing an update comprises forwarding the data from the source real address and tagging the data with the destination effective address corresponding to the destination real address.

14. The method of claim 8, further comprising:

determining when the destination effective address of the AMM ST instruction is and effective address that is represented within the lower level cache; and

responding to the addresses being the same by performing one of;

triggering an automatic update of the data within the lower level cache within cache lines addressed with the corresponding effective address; and

triggering an update of the cache state for the cache lines to an invalid (I) state, to force the cache to load coherent data from the memory when the data associated with the effective address is requested by the processor.

12. The method of Clan 8, wherein the performing an update comprises:

evaluating a size of the data being moved relative to a size of the at least one lower level cache; and

forwarding only a first subset of the data to the at least one lower level cache when the size of the data exceeds a threshold size which would overrun the lower level cache.

13. The method of claim 12, wherein:

the at least one lower level cache includes an L2 cache and an L3 cache; and

said forwarding only a first subset of the data comprises;

forwarding one or more L2 cache line sized data to the L2 cache from the first portion of the data being moved;

forwarding one or more L3 cache line sized data to the L3 cache from a sequentially following second portion of data being moved; and

forwarding remaining data to the memory;

wherein not all data being moved are placed within the L2 and L3 cache and wherein the L2 and L3 caches are not filled with data from the data move operation.