Strain Bars in Stressed Layers of MOS Devices

• US 20090230439A1
• Filed: 03/13/2008
• Published: 09/17/2009
• Est. Priority Date: 03/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yen-Sen, Yang, Sheng-Jier, Cao, Min, Lin, Chung-Te
• Granted Patent: US 7,943,961 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Claims

1. A semiconductor structure comprising:

an active region;

a gate strip overlying the active region;

a metal-oxide-semiconductor (MOS) device, wherein a portion of the gate strip forms a gate of the MOS device, and wherein a portion of the active region forms a source/drain region of the MOS device;

a stressor region over the MOS device; and

a stressor-free region inside the stressor region and outside theregion over the active region.

2. The semiconductor structure of claim 1, wherein the stressor-free region is adjacent to an edge of the active region, and has a length greater than a path of a detrimental stress applied to a channel of the MOS device.

3. The semiconductor structure of claim 1, wherein the stressor-free region is in a path of a detrimental inherent stress in the stressor region, and wherein the stressor region is free from strain bars therein in paths of beneficial inherent stresses in the stressor region.

4. The semiconductor structure of claim 3, wherein the MOS device is a PMOS device, the stressor region has a compressive stress, and wherein the stressor-free region is in the path of a stress in a gate width direction of the MOS device.

5. The semiconductor structure of claim 3, wherein the MOS device is a PMOS device, the stressor region has a tensile stress, and wherein the stressor-free region is in the path of an inherent stress in a gate length direction of the MOS device.

6. The semiconductor structure of claim 3, wherein the MOS device is an NMOS device, the stressor region has a compressive stress, and wherein the stressor-free region is in the path of an inherent stress in a gate width direction of the MOS device.

7. The semiconductor structure of claim 6 further comprising an additional stressor-free region in the path of an inherent stress in a gate length direction of the MOS device.

8. The semiconductor structure of claim 1 further comprising an inter-layer dielectric (ILD) over the stressor region, wherein the ILD extends into the stressor-free region.

9. The semiconductor structure of claim 1 further comprising:

an ILD over the stressor region; and

a dummy contact plug extends into the ILD and the stressor-free region.

10. The semiconductor structure of claim 1, wherein the stressor-free region comprises a dielectric material having an opposite type of inherent stress than the stressor region.

11. A semiconductor structure comprising:

a semiconductor substrate;

an active region in the semiconductor substrate;

an isolation region in the semiconductor substrate and adjoining the active region;

a metal-oxide-semiconductor (MO S) device comprising;

a gate electrode over the active region; and

a source region and a drain region on opposing sides of the gate electrode, wherein the source and drain regions overlap portions of the active region;

a stressor layer over the active region and the isolation region;

a stressor-free region encircled by the stressor layer and directly overlying the isolation region; and

a first strain bar in the stressor-free region.

12. The semiconductor structure of claim 11, wherein the first strain bar and a nearest boundary of the active region has a distance of less than about 0.3 μ

m.

13. The semiconductor structure of claim 11, wherein the first strain bar has a stress type opposite to a stress type of the stressor layer.

14. The semiconductor structure of claim 11, wherein the first strain bar is substantially parallel to a nearest edge of the active region, and wherein the first strain bar has a length greater than about a path of a detrimental stress applied to a channel of the MOS device.

15. The semiconductor structure of claim 11 further comprising a second strain bar on an opposite side of the active region than the first strain bar, wherein the second strain bar is encircled by the stressor layer and directly over a second isolation region.

16. The semiconductor structure of claim 15 further comprising a third strain bar substantially perpendicular to the first and the second strain bars, wherein the third strain bar is encircled by the stressor layer and over a third isolation region.

17. The semiconductor structure of claim 15, wherein the first and the second strain bars form a closed loop with additional strain bars, and wherein the additional strain bars are encircled by the stressor layer and over a continuous isolation region comprising the first and the second isolation regions.

18. A semiconductor structure comprising:

a semiconductor substrate;

an active region in the semiconductor substrate;

a shallow trench isolation (STI) region in the semiconductor substrate and adjoining the active region;

a metal-oxide-semiconductor (MOS) device comprising;

a gate electrode over the active region; and

a source region and a drain region on opposing sides of the gate electrode, wherein the source and the drain regions overlap portions of the active region;

a contact etch stop layer (CESL) over the active region and the STI region;

a stressor-free region overlying the isolation region, where the stressor-free region is encircled by the CESL;

a strain bar filling the stressor-free region;

an inter-layer dielectric (ILD) over the CESL; and

a contact plug in the ILD and contacting one of the source and drain regions.

19. The semiconductor structure of claim 18, wherein the ILD extends into the stressor-free region to form the strain bar.

20. The semiconductor structure of claim 18 further comprising a dummy contact plug in the ILD, wherein the dummy contact plug extends into the stressor-free region to form the strain bar.