Strain bars in stressed layers of MOS devices
First Claim
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1. A semiconductor structure comprising:
- an active region;
a gate strip overlying the active region;
a metal-oxide-semiconductor (MOS) device, wherein a portion of the gate strip forms a gate of the MOS device, and wherein a portion of the active region forms a source/drain region of the MOS device;
a stressor region over the MOS device;
a stressor-free region inside the stressor region and outside the region over the active region;
an ILD over the stressor region; and
a dummy contact plug extending into the ILD and into the stressor-free region.
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Abstract
A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.
208 Citations
19 Claims
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1. A semiconductor structure comprising:
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an active region; a gate strip overlying the active region; a metal-oxide-semiconductor (MOS) device, wherein a portion of the gate strip forms a gate of the MOS device, and wherein a portion of the active region forms a source/drain region of the MOS device; a stressor region over the MOS device; a stressor-free region inside the stressor region and outside the region over the active region; an ILD over the stressor region; and a dummy contact plug extending into the ILD and into the stressor-free region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor structure comprising:
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a semiconductor substrate; an active region in the semiconductor substrate; an isolation region in the semiconductor substrate and adjoining the active region; a metal-oxide-semiconductor (MOS) device comprising; a gate electrode over the active region; and a source region and a drain region on opposing sides of the gate electrode, wherein the source and drain regions overlap portions of the active region; a stressor layer over the active region and the isolation region; a stressor-free region directly overlying the isolation region; and an inter-layer dielectric (ILD) over the stressor layer, wherein a portion of the ILD extends into the stressor-free region to form a first strain bar in the stressor-free region, and wherein a bottom surface of the portion of the ILD extends into the stressor-free region and contacts a top surface of the isolation region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor structure comprising:
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a semiconductor substrate; an active region in the semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate and adjoining the active region; a metal-oxide-semiconductor (MOS) device comprising; a gate electrode over the active region; and a source region and a drain region on opposing sides of the gate electrode, wherein the source and the drain regions overlap portions of the active region; a contact etch stop layer (CESL) over the active region and the STI region; a stressor-free region overlying the isolation region, wherein the stressor-free region has a lengthwise direction perpendicular to a lengthwise direction of the gate electrode, and wherein no stressor-free region having a lengthwise direction parallel to the lengthwise direction of the gate electrode is formed adjacent the gate electrode; a strain bar filling the stressor-free region; an inter-layer dielectric (ILD) over the CESL; and a contact plug in the ILD and contacting one of the source and drain regions. - View Dependent Claims (17, 18, 19)
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Specification