Correlated double sampling technique

• US 20090237121A1
• Filed: 03/19/2008
• Published: 09/24/2009
• Est. Priority Date: 03/19/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Surendranath, Nagesh, Mandal, Dipankar
• Granted Patent: US 7,667,501 B2
• Time in Patent Office: Days
• US Class Current: 327/96
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

Claims

1. A sampling circuit comprising:

a node;

a driver circuit to drive said node according to a voltage level on an input terminal, an input signal being provided on said input terminal in a second phase and said input signal not being provided on said input terminal in a first phase such that an offset voltage is present on said node in said first phase and a sum of said input signal and said offset voltage is present on said node in said second phase;

a first capacitor coupled to be charged by a voltage level at said node in said first phase and to be disconnected from said node in said second phase such that said first capacitor is charged to said offset voltage, said first capacitor having a first capacitance;

a second capacitor to be charged by the voltage level at said node in said second phase and to be disconnected from said node in said first phase such that said second capacitor is charged to said sum, said second capacitor having a second capacitance;

a first amplifier having one of said first capacitor and said second capacitor to be coupled between an input terminal and an output terminal of said first amplifier and the other one of said first capacitor and said second capacitor being coupled between said input terminal and a reference terminal during a third phase,

wherein said first capacitance is not equal to said second capacitance.

2. The sampling circuit of claim 1, wherein said second capacitor is coupled between the input terminal and the output terminal of said first amplifier, and said first capacitor is coupled between said input terminal and said reference terminal during said third phase.

3. The sampling circuit of claim 2, wherein said first capacitance is substantially less than said second capacitance such that the feedback factor of said first amplifier during said third phase is approximately equal to one.

4. The sampling circuit of claim 3, wherein said input signal is a charge, wherein said driver circuit is a charge to voltage converter.

5. The sampling circuit of claim 4, wherein said charge to voltage converter comprises:

a second amplifier having a third capacitor coupled between an input terminal and an output terminal of said second amplifier in said first phase and a fourth capacitor coupled between said input terminal and said output terminal of said second amplifier in said second phase,

wherein the capacitance of said third capacitor is not equal to the capacitance of said fourth capacitor.

6. The sampling circuit of claim 5, wherein said fourth capacitor is realized by a parallel combination of said third capacitor and a fifth capacitor.

7. The sampling circuit of claim 5, wherein the capacitance of said third capacitor (C3) is substantially less than the capacitance of said fourth capacitor (C4).

8. The sampling circuit of claim 7, wherein C4=G*C3, wherein G is the ratio of said second capacitance to said first capacitance.

9. A device comprising:

a sampling circuit to provide samples of an input signal, said sampling circuit comprising;

means for sampling an offset voltage at a node on to a first capacitor in a first phase;

means for sampling a sum of said offset voltage and a voltage level representing said input signal also at said node on to a second capacitor in a second phase; and

means for generating a difference of said sum and said offset voltage in a third phase by providing said first capacitor between an input terminal of an amplifier and a reference terminal, and said second capacitor between said input terminal and an output terminal of said amplifier,

wherein the capacitance of said first capacitor is less than the capacitance of said second capacitor,

said difference representing a sample of said input signal;

an analog to digital converter (ADC) to generate a digital code from said sample; and

a processor to process said digital code.

10. The device of claim 9, wherein said second capacitor is coupled between the input terminal and the output terminal of said first amplifier, and said first capacitor is coupled between said input terminal and said reference terminal during said third phase.

11. The device of claim 10, wherein said first capacitance is substantially less than said second capacitance such that the feedback factor of said first amplifier during said third phase is approximately equal to one.

12. The device of claim 11, wherein said input signal is a charge, wherein said driver circuit is a charge to voltage converter.

13. The device of claim 12, wherein said charge to voltage converter comprises:

a second amplifier having a third capacitor coupled between an input terminal and an output terminal of said second amplifier in said first phase and a fourth capacitor coupled between said input terminal and said output terminal of said second amplifier in said second phase,

wherein the capacitance of said third capacitor is not equal to the capacitance of said fourth capacitor.

14. The device of claim 13, wherein said fourth capacitor is realized by a parallel combination of said third capacitor and a fifth capacitor.

15. The device of claim 13, wherein the capacitance of said third capacitor (C3) is substantially less than the capacitance of said fourth capacitor (C4).

16. The device of claim 15, wherein C4=G*C3, wherein G is the ratio of said second capacitance to said first capacitance.

17. A method of sampling an input signal using correlated double sampling (CDS) technique, wherein a node providing said input signal also contains a non-signal component, said CDS technique comprising:

sampling an offset voltage at a node on to a first capacitor in a first phase;

sampling a sum of said offset voltage and a voltage level representing said input signal also at said node on to a second capacitor in a second phase; and

generating a difference of said sum and said offset voltage in a third phase by providing said first capacitor between an input terminal of an amplifier and a reference terminal, and said second capacitor between said input terminal and an output terminal of said amplifier,

wherein the capacitance of said first capacitor is less than the capacitance of said second capacitor.