Correlated double sampling technique

• US 7,667,501 B2
• Filed: 03/19/2008
• Issued: 02/23/2010
• Est. Priority Date: 03/19/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Surendranath, Nagesh, Mandal, Dipankar
• Primary Examiner(s): Nguyen; Long
• Assistant Examiner(s): Goyal; Shikha
• Application Number:
  US12/051,839
• Publication Number:
  US 20090237121A1
• Time in Patent Office: 706 Days
• Field of Search: 327/91, 327 93- 97, 327/99, 327/554, 341122-125
• US Class Current: 327/94
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

Claims

1. An apparatus comprising:

a charge-to-voltage converter having;

a first operational amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a first capacitor that is coupled to the first input terminal of the first operational amplifier and the first output terminal of the first operational amplifier;

a second capacitor that is coupled to the second input terminal of the first operational amplifier and the second output terminal of the first operational amplifier, wherein the capacitance of the first capacitor is approximately equal to the capacitor of the second capacitor;

a third capacitor that is coupled to the first input terminal of the first operational amplifier;

a fourth capacitor that is coupled to the second input terminal of the first operational amplifier, wherein the capacitance of the third capacitor is approximately equal to the capacitance of the fourth capacitor;

a first switch that is coupled between the third capacitor and the first output terminal of the first operational amplifier;

a second switch that is coupled between the fourth capacitor and the second output terminal of the first operational amplifier;

a third switch that is coupled between the third capacitor and ground; and

a fourth switch that is coupled between the fourth capacitor and ground; and

a correlated double sample (CDS) amplifier having;

a second operational amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a fifth capacitor that is coupled to the second input terminal of the second operational amplifier and to the first output terminal of the first operational amplifier;

a sixth capacitor that is coupled to the first input terminal of the second operational amplifier and to the second output terminal of the first operational amplifier, wherein the capacitance of the fifth capacitor is approximately equal to the capacitance of the sixth capacitor;

a third switch that is coupled to the first output terminal of the second operational amplifier;

a fourth switch that is coupled to the second output terminal of the second operational amplifier;

a fifth switch that is coupled to the first input terminal of the second operational amplifier;

a sixth switch that is coupled to the second input terminal of the second operational amplifier;

a seventh capacitor that is coupled between the third and fifth switches; and

an eighth capacitor that is coupled between the fourth and sixth switches, wherein the capacitance of the seventh capacitor is approximately equal to the capacitance of the eighth capacitor, and wherein the ratio of the capacitance of the third capacitor to the capacitance of the first capacitor is approximately equal to the ratio of the capacitance of the fifth capacitor to the capacitance of the eighth capacitor.

2. The apparatus of claim 1, wherein the CDS amplifier further comprises:

a seventh switch that is coupled to the seventh capacitor and to ground; and

an eighth switch that is coupled to the eighth capacitor and to ground.

3. The apparatus of claim 1, wherein the CDS amplifier further comprises:

a seventh switch that is coupled to the first output terminal of the first operational amplifier;

an eighth switch that is coupled to the second output terminal of the first operational amplifier;

a first resistor that is coupled to the seventh switch and to the fifth capacitor; and

a second resistor that is coupled to the eighth switch and to the sixth capacitor.

4. The apparatus of claim 3, wherein the CDS amplifier further comprises:

a ninth switch that is coupled to the first resistor and to ground; and

a tenth switch that is coupled to the second resistor and to ground.

5. The apparatus of claim 1, wherein the CDS amplifier further comprises:

a seventh switch that is coupled between the fifth capacitor and the second input terminal of the second operational amplifier; and

an eighth switch that is coupled between the sixth capacitor and the first input terminal of the second operational amplifier.

6. The apparatus of claim 1, wherein the charge-to-voltage converter further comprises:

a seventh switch that is coupled in parallel to the first capacitor; and

an eighth switch that is coupled in parallel to the second capacitor.