HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME

• US 20090261343A1
• Filed: 06/03/2009
• Published: 10/22/2009
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mahajani, Maitreyee, Herner, S. Brad
• Granted Patent: US 8,004,033 B2
• Time in Patent Office: Days
• US Class Current: 257/74
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

Claims

1. A method to form a nonvolatile memory cell, the method comprising:

i) forming a first conductor at a first height above a substrate;

ii) forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type;

iii) forming a first antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and

iv) forming a second conductor above the first antifuse.

2. The method of claim 1, wherein the step of forming the first semiconductor element comprises:

after the step of forming the first conductor, depositing a semiconductor layer stack on the first conductor; and

patterning and etching the semiconductor layer stack to form the first pillar-shaped semiconductor element.

3. The method of claim 2, wherein depositing the semiconductor layer stack comprises depositing polycrystalline silicon.

4. The method of claim 1, wherein the substrate comprises monocrystalline silicon.

5. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

6. The method of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

7. The method of claim 1, wherein the third heavily doped layer is doped by ion implantation.

8. The method of claim 1, wherein the first heavily doped layer is doped by in situ doping.

9. The method of claim 1, wherein forming the first conductor comprises:

depositing a first tungsten layer; and

patterning and etching the first tungsten layer to form the first conductor.

10. The method of claim 1, wherein the first antifuse comprises an oxide layer.

11. The method of claim 10, wherein the oxide layer comprises silicon dioxide.

12. A monolithic three dimensional memory array comprising:

a plurality of substantially parallel first conductors above a substrate, the first conductors not comprising monocrystalline silicon;

a plurality of first semiconductor elements above the first conductors, each first semiconductor element comprising a first heavily doped layer of a first conductivity type, a second lightly doped layer, and a third heavily doped layer of a second conductivity type;

a plurality of first antifuse layers, each first antifuse layer formed above one of the plurality of first semiconductor elements; and

a plurality of substantially parallel second conductors, the second conductors above the plurality of first antifuse layers.

13. The monolithic three dimensional memory array of claim 12, wherein the substrate comprises monocrystalline silicon.

14. The monolithic three dimensional memory array of claim 12, wherein the first conductors or the second conductors comprise tungsten.

15. The monolithic three dimensional memory array of claim 12, wherein the first semiconductor elements are vertically oriented pillars.

16. The monolithic three dimensional memory array of claim 12, wherein the first semiconductor elements comprise polycrystalline silicon.

17. The monolithic three dimensional memory array of claim 12, wherein the first antifuse layers comprise an oxide.

18. The monolithic three dimensional memory array of claim 17, wherein the oxide comprises silicon dioxide.

19. The monolithic three dimensional memory array of claim 12, further comprising a plurality of second semiconductor elements above the plurality of substantially parallel second conductors.

20. The monolithic three dimensional memory array of claim 19, further comprising a plurality of third conductors formed above the plurality of second semiconductor elements.

21. The monolithic three dimensional memory array of claim 12, further comprising a plurality of memory cells, each memory cell comprising a portion of one of the first conductors, one of the first semiconductor elements, and a portion of one of the second conductors.

22. The monolithic three dimensional memory array of claim 12, wherein the first conductors extend in a first direction, and the second conductors extend in a second direction, the second direction different from the first direction.

23. The monolithic three dimensional memory array of claim 22, wherein the second direction is substantially perpendicular to the first direction.

24. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate;

forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors, each of the first plurality of semiconductor elements comprising a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer, the third heavily doped layer having a second conductivity type opposite the first conductivity type; and

forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements.

25. The method of claim 24, wherein forming the first plurality of substantially parallel, substantially coplanar conductors comprises:

depositing a first conductive layer;

patterning and etching the first conductive layer to form the first plurality of substantially parallel, substantially coplanar conductors;

depositing a first dielectric material over and between the first plurality of substantially parallel, substantially coplanar conductors; and

planarizing to expose tops of the first plurality of substantially parallel, substantially coplanar conductors separated by the first dielectric material.

26. The method of claim 25, wherein forming the first plurality of semiconductor elements comprises:

after planarizing, depositing a first semiconductor layer stack on the first dielectric material and the first plurality of substantially parallel, substantially coplanar conductors;

patterning and etching the first semiconductor layer stack to form the first plurality of semiconductor elements;

depositing a second dielectric material on and between the first plurality of semiconductor elements; and

planarizing to expose tops of the first plurality of semiconductor elements.

27. The method of claim 26, wherein depositing the first semiconductor layer stack comprises depositing polycrystalline silicon.

28. The method of claim 26, wherein each of the first plurality of semiconductor elements is pillar-shaped.

29. The method of claim 24, wherein the third heavily doped layer of each of the first plurality of semiconductor elements is doped by ion implantation.

30. The method of claim 24, wherein the first heavily doped layer of each of the first plurality of semiconductor elements is doped by in situ doping.

31. The method of claim 24, further comprising forming a second plurality of semiconductor elements above the second plurality of substantially parallel, substantially coplanar conductors.

32. The method of claim 31, further comprising forming a third plurality of substantially parallel, substantially coplanar conductors above the second plurality of semiconductor elements.

33. The method of claim 24, further comprising forming a plurality of first antifuse layers disposed between the first plurality of semiconductor elements and the second plurality of substantially parallel, substantially coplanar conductors.

34. The method of claim 33, wherein forming the first antifuse layers comprises forming oxide layers.

35. The method of claim 34, wherein forming oxide layers comprises oxidizing a portion of the third heavily doped layer of each of the first plurality of semiconductor elements.

36. The method of claim 24, wherein the first conductivity type is N-type and the second conductivity type is P-type.

37. The method of claim 24, wherein the first conductivity type is P-type and the second conductivity type is N-type.