High-density nonvolatile memory

• US 8,004,033 B2
• Filed: 06/03/2009
• Issued: 08/23/2011
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mahajani, Maitreyee, Herner, S. Brad
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US12/477,216
• Publication Number:
  US 20090261343A1
• Time in Patent Office: 811 Days
• Field of Search: 257/296, 257208-209, 257257-258
• US Class Current: 257/318
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

Claims

1. A monolithic three dimensional memory array comprising:

a plurality of substantially parallel first conductors above a substrate, the first conductors not comprising monocrystalline silicon;

a plurality of first semiconductor elements above the first conductors, each first semiconductor element comprising a first heavily doped layer of a first conductivity type, a second lightly doped layer, and a third heavily doped layer of a second conductivity type;

a plurality of first antifuse layers, each first antifuse layer formed above one of the plurality of first semiconductor elements; and

a plurality of substantially parallel second conductors, the second conductors above the plurality of first antifuse layers.

2. The monolithic three dimensional memory array of claim 1, wherein the substrate comprises monocrystalline silicon.

3. The monolithic three dimensional memory array of claim 1, wherein the first conductors or the second conductors comprise tungsten.

4. The monolithic three dimensional memory array of claim 1, wherein the first semiconductor elements are vertically oriented pillars.

5. The monolithic three dimensional memory array of claim 1, wherein the first semiconductor elements comprise polycrystalline silicon.

6. The monolithic three dimensional memory array of claim 1, wherein the first antifuse layers comprise an oxide.

7. The monolithic three dimensional memory array of claim 6, wherein the oxide comprises silicon dioxide.

8. The monolithic three dimensional memory array of claim 1, further comprising a plurality of second semiconductor elements above the plurality of substantially parallel second conductors.

9. The monolithic three dimensional memory array of claim 8, further comprising a plurality of third conductors formed above the plurality of second semiconductor elements.

10. The monolithic three dimensional memory array of claim 1, further comprising a plurality of memory cells, each memory cell comprising a portion of one of the first conductors, one of the first semiconductor elements, and a portion of one of the second conductors.

11. The monolithic three dimensional memory array of claim 1, wherein the first conductors extend in a first direction, and the second conductors extend in a second direction, the second direction different from the first direction.

12. The monolithic three dimensional memory array of claim 11, wherein the second direction is substantially perpendicular to the first direction.

13. The monolithic three dimensional memory array of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

14. The monolithic three dimensional memory array of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

15. The monolithic three dimensional memory array of claim 1, wherein each third heavily doped layer is doped by ion implantation.

16. The monolithic three dimensional memory array of claim 1, wherein each first heavily doped layer is doped by in situ doping.