Dynamic Core Pool Management

• US 20100037038A1
• Filed: 08/06/2008
• Published: 02/11/2010
• Est. Priority Date: 08/06/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McCreary, Hye-Young, Geissler, Andrew, Rawson, Freeman L. III, Bieswanger, Andreas
• Granted Patent: US 8,892,916 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments that dynamically manage core pools are disclosed. Various embodiments involve measuring the amount of a computational load on a computing device. One way of measuring the load may consist of executing a number of instructions, in a unit of time, with numerous cores of the computing device. These embodiments may compare the number of instructions executed with specific thresholds. Depending on whether the number of instructions is higher or lower than the thresholds, the computing devices may respond by activating and deactivating cores of the computing devices. By limiting execution of instructions of the computing device to a smaller number of cores and switching one or more cores to a lower power state, the devices may conserve power.

Claims

1. A method, comprising:

executing, via a first number of cores of a computing device, a number of instructions in a unit of time;

detecting that the number of instructions executed is less than a threshold;

limiting execution of instructions of the computing device from the first number of cores to a second number of cores in response to the detecting that the number of instructions executed is below the threshold, wherein the second number is less than the first number; and

switching a core of the first number of cores from a first power state to a second power state, wherein power consumption of the second power state is less than power consumption of the first power state.

2. The method of claim 1, further comprising performing at least one of dynamic voltage scaling and dynamic frequency scaling of at least one core of the computing device within a second unit of time, wherein the second unit of time is smaller than the unit of time.

3. The method of claim 2, wherein the first unit of time is between 1 second and 10 seconds, inclusive, and the second unit of time is 2 seconds or less.

4. The method of claim 1, further comprising executing a second number of instructions in a second unit of time and, in response to the second number being greater than a second threshold, switching at least one core from a third power state to a fourth power state, wherein power consumption of the fourth power state is greater than power consumption of the third power state.

5. The method of claim 1, wherein the limiting execution of instructions from the first number of cores to the second number of cores comprises limiting execution of instructions from a first number of integrated circuits (ICs) to a second number of ICs, wherein the second number is less than the first number.

6. The method of claim 5, further comprising switching an IC of the first number of ICs from a first IC state to a second IC state, wherein power consumption of the second IC state is less than power consumption of the first IC state.

7. The method of claim 1, wherein the limiting execution of instructions from the first number of cores to the second number of cores comprises changing mapping of a virtual processor unit of the first number of cores.

8. An apparatus, comprising:

a demand determiner to determine a demand of a pool of cores, wherein the demand comprises execution of a number of instructions in a unit of time by the pool of cores;

a core switcher to switch power states of one or more cores of the pool of cores; and

a power controller to cause the core switcher to switch a core of the pool of cores from a first power state to a second power state in response to the demand determiner determining the demand is less than a threshold.

9. The apparatus of claim 8, further comprising at least one of a dynamic voltage scaler to scale a voltage of the core and a dynamic frequency scaler to scale a frequency of the core.

10. The apparatus of claim 9, wherein the at least one of the dynamic voltage scaler and the dynamic frequency scaler is arranged to operate independently of the core switcher.

11. The apparatus of claim 8, further comprising a virtual processing unit controller to change a number of virtual processing units allocated to the pool of cores, wherein the virtual processing unit controller is arranged to change the number in response the determined demand.

12. The apparatus of claim 11, wherein the virtual processing unit controller is arranged to change allocation of virtual processing units from a first number of integrated circuits (ICs) to a second number of ICs in response to the demand determiner determining the demand is less than the threshold, wherein the second number of ICs is less than the first number of ICs.

13. The apparatus of claim 11, wherein the virtual processing unit controller comprises a dynamic logic partitioning module.

14. The apparatus of claim 11, wherein the virtual processing unit controller is arranged to change the number to meet a performance requirement of an operating system image.

15. The apparatus of claim 8, wherein the core switcher is arranged to switch the core from the second power state in response to the demand determiner determining the demand is greater than a second threshold, wherein further the apparatus comprises a server.

16. The apparatus of claim 15, further comprising a virtual processing unit controller to increase a number of virtual processing units available to execute instructions in response the switching of the core.

17. The apparatus of claim 8, wherein the demand determiner is arranged to determine the demand by counting a number of cycles of the pool.

18. A computer program product comprising:

a computer readable storage medium including instructions that, when executed by at least one processor;

execute a number of instructions in a unit of time via a plurality of cores;

detect that the number of instructions executed is less than a threshold; and

change a power state of a core in the plurality of cores from a first power state to a second power state, wherein the change is in response to the detection of the number being less than the threshold, wherein further power consumption of the second power state is lower than power consumption of the first power state.

19. The computer program product of claim 18, further comprising instructions that change mapping of virtual processing units for the plurality of cores in response to the detection of the number being less than the threshold.

20. The computer program product of claim 19, further comprising instructions that assign hardware threads and cores to partitions with spans greater than one in response to the detection of the number being less than the threshold, wherein the assignment of the hardware threads and the cores is to localize the partitions to a contiguous set of cores.