Dynamic core pool management

• US 8,892,916 B2
• Filed: 08/06/2008
• Issued: 11/18/2014
• Est. Priority Date: 08/06/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bieswanger, Andreas, Geissler, Andrew, McCreary, Hye-Young, Rawson, Freeman L. III
• Primary Examiner(s): Brown, Michael J
• Application Number:
  US12/186,680
• Publication Number:
  US 20100037038A1
• Time in Patent Office: 2,295 Days
• Field of Search: 713/300, 713/320, 713/330, 713/340, 718/102, 718/105
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Mechanisms for dynamically managing core pools are provided. The mechanisms measure the amount of a computational load on a computing device. One way of measuring the load may consist of executing a number of instructions, in a unit of time, with numerous cores of the computing device. The mechanisms compare the number of instructions executed with specific thresholds. Depending on whether the number of instructions is higher or lower than the thresholds, the computing devices may respond by activating and deactivating cores of the computing devices. By limiting execution of instructions of the computing device to a smaller number of cores and switching one or more cores to a lower power state, the devices may conserve power.

Claims

1. A method, comprising:

detecting, by a virtual machine manager of a computing device, that a number of instructions executed by a plurality of virtual machines in a unit of time is less than a threshold;

limiting, by the virtual machine manager, execution of instructions of the plurality of virtual machines from the first number of cores to a second number of cores in response to the detecting that the number of instructions executed is below the threshold, wherein the second number is less than the first number, wherein the limiting execution of instructions from the first number of cores to the second number of cores comprises the virtual machine manager changing mapping of a virtual processor unit of the first number of cores; and

switching, by the virtual machine manager, a core of the first number of cores from a first power state to a second power state, wherein power consumption of the second power site is less than power consumption of the first power state.

2. The method of claim 1, further comprising performing, at least one of dynamic voltage scaling and dynamic frequency scaling of at least one core of the computing device within a second unit of time, wherein the second unit of time is smaller than the unit of time.

3. The method of claim 2, wherein the unit of time is between 1 second and 10 seconds, inclusive, and the second unit of time is 2 seconds or less.

4. The method of claim 1, further comprising executing a second number of instructions in a second unit of time and, in response to the second number being greater than a second threshold, switching at least one core from a third power state to a fourth power state, wherein power consumption of the fourth power state is greater than power consumption of the third power state.

5. The method of claim 1, wherein the limiting execution of instructions from the first number of cores to the second number of cores further comprises limiting execution of instructions from a first number of integrated circuits (ICs) to a second number of ICs responsive to the changing mapping of the virtual processor unit of the first number of cores resulting in at least one of the first number of ICs being inactive, wherein the second number of ICs is less than the first number of ICs, wherein the first number of ICs comprises the first number of cores, and wherein the second number of ICs comprises the second number of cores.

6. The method of claim 5, further comprising switching an IC of the first number of ICs from a first IC state to a second IC state, wherein power consumption of the second IC state is less than power consumption of the first IC state.

7. An apparatus, comprising:

a pool of cores;

a demand determiner in a virtual a machine manager in a computing device to determine a demand of a first number of cores within the pool of cores of the computing device, wherein the demand comprises execution of a number of instructions by a plurality of virtual machines in a unit of time by the first number of cores;

a core switcher in the virtual machine manager to switch power states of one or more cores of the first number of cores;

a power controller in the virtual machine manager to limit execution of instructions of the plurality of virtual machines from the first number of cores to a second number of cores in response to the detecting that the number of instructions executed is below the threshold, wherein the second number is less than the first number and to cause the core switcher to switch a core of the first number of cores from a first power state to a second power state in response to the demand determiner determining the demand is less than a threshold; and

a virtual processing unit controller in the virtual machine manager to change a number of virtual processing units allocated to the pool of cores, wherein the virtual processing unit controller is arranged to change the number in response the determined demand.

8. The apparatus of claim 7, further comprising at least one of a dynamic voltage scaler to scale a voltage of the core and a dynamic frequency scaler to scale a frequency of the core.

9. The apparatus of claim 8, wherein the at least one of the dynamic voltage scaler and the dynamic frequency scaler is arranged to operate independently of the core switcher.

10. The apparatus of claim 7, wherein the virtual processing unit controller is arranged to change allocation of virtual processing units from a first number of integrated circuits (ICs) to a second number of ICs responsive to the changing mapping of the virtual processor unit of the first number of cores resulting in at least one of the first number of ICs being inactive, wherein the second number of ICs is less than the first number of ICs, wherein the first number of ICs comprises the first number of cores, and wherein the second number of ICs comprises the second number of cores.

11. The apparatus of claim 7, wherein the virtual processing unit controller comprises a dynamic logic partitioning module.

12. The apparatus of claim 7, wherein, the virtual processing unit controller is arranged to change the number to meet a performance requirement of an operating system image.

13. The apparatus of claim 7, wherein the core switcher is arranged to switch the core from the second power state in response to the demand determiner determining the demand is greater than a second threshold, wherein further the apparatus comprises a server.

14. The apparatus of claim 13, the virtual processing unit controller to increase a number of virtual processing units available to execute instructions in response the switching of the core.

15. The apparatus of claim 7, wherein the demand determiner is arranged to determine the demand by counting a number of cycles of the pool.

16. A computer program product comprising

a non-transitory computer readable storage medium including instructions that, when executed by at least one processor:

detect, by a virtual machine manager of a computing device, that a number of instructions executed by a plurality of Virtual machines in a unit of time is less than a threshold;

limit, by the virtual machine manager, execution of instructions of the plurality of virtual machines from the first number of cores to a second number of cores in response to the detecting that the number of instructions executed is below the threshold, wherein the second number is less than the first number, wherein the limiting execution of instructions from the first number of cores to the second number of cores comprises the virtual machine manager changing mapping of a virtual processor unit of the first number of cores; and

change, by the virtual machine manager, a power state of a core in the first plurality of cores from a first power state to a second power state, wherein the change is in response to the detection of the number being less than the threshold, wherein power consumption of the second power state is lower than power consumption of the first power state.

17. The computer program product of claim 16, further comprising instructions that assign hardware threads and cores to partitions with spans greater than one in response to the detection of the number being less than the threshold, wherein the assignment of the hardware threads and the cores is to localize the partitions to a contiguous set of cores.

18. The computer program product of claim 16, wherein the limiting execution of instructions from the first number of cores to the second number of cores further comprises limiting execution of instructions from a first number of integrated circuits (ICs) to a second number of ICs responsive to the changing mapping of the virtual processor unit of the first number of cores resulting in at least one of the first number of ICs being inactive, wherein the second number of ICs is less than the first number of ICs, wherein the first number of ICs comprises the first number of cores, and wherein the second number of ICs comprises the second number of cores.

19. The computer program product of claim 18, wherein the limiting execution of instructions from the first number of cores to the second number of cores further comprises switching an IC of the first number of ICs from a first IC state to a second IC state, wherein power consumption of the second IC state is less than power consumption of the first IC state.

20. The computer program product of claim 16, further comprising further comprising instructions that perform dynamic voltage scaling and dynamic frequency scaling of at least one core of the computing device within a second unit of time, wherein the second unit of time is smaller than the unit of time.