Package for Semiconductor Devices

• US 20100140627A1
• Filed: 10/08/2009
• Published: 06/10/2010
• Est. Priority Date: 01/10/2005
• Status: Abandoned Application

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Pabisz, Marek K., Peres, Boris, Shelton, Bryan S., Zhu, TingGang, Liu, Linlin
• Application Number:
  US12/575,717
• Publication Number:
  US 20100140627A1
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.

Claims

1. An insulated semiconductor packaging device comprising:

a leadframe comprising a header connected to a mounting bracket;

at least one semiconductor die mounted to the header of the leadframe;

at least two spaced external conductors extending from said header such that the at least two spaced external conductors are not electrically connected to the header of the leadframe, said one of the at least two spaced external conductor is substantially parallel to the other of the at least two spaced external conductors;

at least a first bonding wire being electrically connected between the die and one of the at least two spaced external conductors not electrically connected to the leadframe and at least a second bonding wire being electrically connected between the die and the other of the at least two spaced external conductors not electrically connected to the header of the leadframe so that the die is electrically insulated from the leadframe; and

a housing enclosing said die and said at least first and second bonding wires, said housing providing mechanical support to the at least two spaced external conductors.

2. The device of claim 1 wherein said one of the at least two spaced external conductors having a first wire bonding post at one end and the other of the at least two spaced external conductors having a second wire bonding post at one end.

3. The device of claim 2 wherein said at least first bonding wire extends from said at least one semiconductor die to said first wire bonding post and said second bonding wire extends from said die to said second wire bonding post.

4. The device of claim 3 wherein said housing encloses said first and second wire bonding posts.

5. The device of claim 1 wherein said housing is a molded plastic material.

6. The device of claim 1 further comprising a third spaced external conductor extending parallel to the at least two spaced external conductors, wherein said third spaced external conductor is connected to the header via a metal.

7. A device as defined in claim 1, wherein said at least first and second bonding wires have at least five mil thickness.

8. A device as defined in claim 1, wherein said at least one semiconductor die is directly attached to the housing by solder or thermally conductive epoxy.

9. The device of claim 1 wherein said at least one semiconductor die is at least one diode.

10. The device of claim 1 wherein said at least one semiconductor die is at least one transistor.

11. The device of claim 1 wherein said semiconductor dies are a combination of at least one diode and at least one transistor.

12. A device as defined in claim 1 wherein said at least one semiconductor die having a top surface and a bottom surface, said top surface including a planar semiconductor layer and said bottom surface including a sapphire substrate.

13. The device of claim 12 wherein said planar semiconductor layer comprising a lower semiconductor layer and an upper semiconductor layer disposed over a portion of said lower semiconductor layer, said lower semiconductor layer and said upper semiconductor layer being of the same conductivity type and said lower semiconductor layer being more highly doped than said upper semiconductor layer.

14. A device as defined in claim 13, wherein said upper and lower semiconductor layers are composed of gallium nitride based material.

15. The device of claim 13 wherein said at least one semiconductor die is at least one diode comprising an anode formed on the upper semiconductor layer and a cathode formed on portions of a lower semiconductor layer.

16. The device of claim 15 further comprising a dielectric layer formed on the lower and upper semiconductor layers devoid of the anode and the cathode.

17. The device of claim 13, wherein said upper semiconductor layer is composed of aluminum gallium nitride and the lower semiconductor layer is composed of gallium nitride.

18. The device of claim 13 wherein said at least one semiconductor die is at least one transistor comprising a gate electrode formed on the upper semiconductor layer, a source electrode and a drain electrode are formed through the upper semi-conductor layer onto the lower semiconductor layer.

19. The device of claim 17 further comprising a dielectric layer formed on the upper semiconductor layer devoid of the gate, the source and the drain electrodes.

20. The device of claim 1 wherein rear side of the header provides for a direct thermal contact.