APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE TO BE TESTED

• US 20100194423A1
• Filed: 09/26/2008
• Published: 08/05/2010
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakagawa, Yoshihiro, Tago, Masamoto
• Application Number:
  US12/679,959
• Publication Number:
  US 20100194423A1
• Time in Patent Office: Days
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Provided is a semiconductor testing apparatus which can perform batch test of semiconductor wafers. In the semiconductor testing apparatus, an LSI apparatus for conducting a test and which provided with a circuit and an electrode for transmitting noncontact signals, and a probe card to which a contact-type probe pin is attached are separately arranged. The semiconductor testing apparatus is provided with a recognition unit for precisely aligning the electrodes of the LSI apparatus for conducting a test, the LSI wafer to be tested and the probe card. The LSI apparatus for conducting a test and a probe pin of the probe card are mounted on a stage or a pressurizing head, and contact can be made to sandwich an LSI wafer to be tested, from both the front surface and the rear surface of the LSI wafer to be tested at the same time.

Claims

1. A semiconductor testing apparatus that tests an LSI wafer to be tested, comprising:

an LSI apparatus for conducting a test comprising an electrode for transmitting a noncontact signal that supplies a signal and power in a noncontact manner to/from the LSI wafer to be tested; and

a contact-type probe pin or electrode,

wherein power and a test signal are supplied by the LSI apparatus for conducting a test and the probe pin or the electrode.

2. The semiconductor testing apparatus according to claim 1, wherein the contact-type electrode is made of an anisotropic conductive material and has a structure whereby pressurization is possible by a pressurizing block attached to a probe card on which the LSI apparatus for conducting a test is mounted via wiring.

3. The semiconductor testing apparatus according to claim 1, wherein a structure is adopted whereby the wiring is mounted on a probe card and the wiring allows pressurization via the anisotropic conductive material.

4. A semiconductor testing apparatus that tests an LSI wafer to be tested, comprising:

an LSI apparatus for conducting a test comprising an electrode for transmitting a noncontact signal that supplies a signal and power in a noncontact manner to/from the LSI wafer to be tested; and

a probe card comprising a contact-type probe pin,

wherein the LSI wafer to be tested is sandwiched by the LSI apparatus for conducting a test and the probe pin, and power and a test signal are supplied to the LSI wafer to be tested from both sides thereof by the LSI apparatus for conducting a test and the probe pin.

5. The semiconductor testing apparatus according to claim 4, wherein either of the LSI apparatus for conducting a test or the probe pin is mounted on a stage, the other is attached to a pressurizing head opposed to the stage configured so as to be able to adjust a distance from the stage, and the LSI wafer to be tested is sandwiched between the LSI apparatus for conducting a test and the probe pin when the pressurizing head moves.

6. The semiconductor testing apparatus according to claim 5, wherein the LSI apparatus for conducting a test is mounted face down on the stage and has a function of securing the LSI wafer to be tested.

7. The semiconductor testing apparatus according to claim 5, wherein a silicon through-hole electrode is formed in the LSI apparatus for conducting a test, mounted face up on the stage and has a function of securing the LSI wafer to be tested.

8. The semiconductor testing apparatus according to claim 4, wherein the probe pin makes contact with a pin used to supply power to the LSI wafer to be tested.

12. The semiconductor testing apparatus according to claim 5, wherein the probe pin makes contact with a pin used to supply power to the LSI wafer to be tested.

13. The semiconductor testing apparatus according to claim 6, wherein the probe pin makes contact with a pin used to supply power to the LSI wafer to be tested.

14. The semiconductor testing apparatus according to claim 7, wherein the probe pin makes contact with a pin used to supply power to the LSI wafer to be tested.

9. A semiconductor device to be tested comprising:

an electrode for transmitting a noncontact signal that supplies a signal or power in a noncontact manner; and

an electrode for contact that transmits a signal and power through contact.

10. A semiconductor device to be tested comprising:

a semiconductor device used as an actual product; and

a power supply semiconductor device whose power supply is shared with said semiconductor device, provided to supply power to the outside.

11. A semiconductor testing method for testing an LSI wafer to be tested, comprising:

sandwiching the LSI wafer to be tested by an LSI apparatus for conducting a test comprising an electrode for transmitting a noncontact signal that supplies a signal and power to/from the LSI wafer to be tested in a noncontact manner and a probe card comprising a contact-type probe pin; and

supplying power and a test signal to the LSI wafer to be tested from both sides thereof by the LSI apparatus for conducting a test and the probe pin.