Interconnection of IC Chips by Flex Circuit Superstructure

• US 20100258952A1
• Filed: 04/07/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Interconnect Portfollo LLC
• Inventors: Fjelstad, Joseph C.
• Application Number:
  US12/755,961
• Publication Number:
  US 20100258952A1
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10356 : Cables
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/222 : Completing of printed circuits by adding non-printed jumper connections printed jumper connections H05K3/4685

Abstract

Integrated circuit chips have top and bottom surfaces. The bottom surfaces comprise a plurality of IC die terminals in flip-chip assembly with fine-pitch terminals formed on the top surface of corresponding interconnection substrate. Each IC chip includes one or more through-silicon vias and/or edge wrap connectors that extend to the top surface, terminating in IC die terminals. Flexible connectors are coupled between the IC die terminals on the top surfaces of corresponding first and second integrated circuit chips. The flexible connectors are preferably controlled impedance, and may include differential pairs, including twisted pairs, coaxial pairs, and broadside pairs. Conductive vias within the interconnection substrates couple the fine-pitch terminals to corresponding next-level terminals on the bottom surface of the respective interconnection substrates. The next level terminals of the interconnection substrates are interconnected with terminals of a printed circuit board.

Claims

1. An electrical assembly comprising:

a first IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a first through-silicon via terminating at a first top-side die terminal formed on the top surface of the first IC chip;

a first interconnection substrate with top and bottom surfaces and a first plurality of fine-pitch terminals disposed on a top surface, the first plurality of fine-pitch terminals of the first interconnection substrate being coupled in flip-chip connection with corresponding bottom-side die terminals of the first IC chip;

a second IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a second through-silicon via terminating at a second top-side die terminal formed on the top surface of the second IC chip;

a second interconnection substrate with top and bottom surfaces and a second plurality of fine-pitch terminals disposed on a top surface, the second plurality of fine-pitch terminals being coupled in flip-chip connection with corresponding bottom-side die terminals of the second IC chip; and

,

a first flexible circuit coupling the first top side die terminal and the second top side die terminal.

2. The electrical assembly of claim 1, the first chip further comprising a third through-silicon via terminating at a third top-side die terminal on the top surface of the first chip.

3. The electrical assembly of claim 2, the second chip further comprising a fourth through-silicon via terminating at a fourth top-side die terminal on the top surface of the second chip;

and,

a second flexible circuit coupling the third top side die terminal and the fourth top side die terminal.

4. The electrical assembly of claim 2, the second chip further comprising a first edge-wrap connector extending from the bottom surface of the second chip to the top surface of the second chip, and terminating at a fourth top-side die terminal on the top surface of the second chip;

and,

a second flexible circuit coupling the third top side die terminal and the fourth top side die terminal.

5. The electrical assembly of claim 1, the first chip further comprising a first edge-wrap connector extending from the bottom surface of the first chip to the top surface of the second chip, and terminating at a third top-side die terminal on the top surface of the first chip;

the second chip further comprising a second edge-wrap connector extending from the bottom surface of the second chip to the top surface of the second chip, and terminating at a fourth top-side die terminal on the top surface of the second chip; and

,

a second flexible circuit coupling the third top side die terminal and the fourth top side die terminal.

6. The electrical assembly of claim 1, wherein the flexible circuit is an exposed bond-wire encapsulated in epoxy.

7. The electrical assembly of claim 1, wherein the flexible circuit comprises a conductive wire formed within a flexible insulating sheath.

8. The electrical assembly of claim 1, wherein the flexible circuit comprises a conductive wire formed within a flexible insulating sheath.

9. The electrical assembly of claim 1 wherein the flexible circuit is coupled to the first top-side die terminal in a wedge bond.

10. The electrical assembly of claim 1 wherein the flexible circuit is coupled to the first top-side die terminal in a ball bond.

11. The electrical assembly of claim 1 wherein the flexible circuit is coupled to the first top-side die terminal in a stitch bond.

12. The electrical assembly of claim 3, wherein the first and second flexible circuit couplings are a differential pair.

13. The electrical assembly of claim 4, wherein the first and second flexible circuit couplings are a differential pair.

14. The electrical assembly of claim 5, wherein the first and second flexible circuit couplings are a differential pair.

15. The electrical assembly of claim 1, further comprising a printed circuit board with a first plurality of circuit board terminals coupled to a second plurality of circuit board terminals through a corresponding plurality of circuit traces wherein;

the first interconnection substrate further comprises a first plurality of package terminals on the bottom surface and a first plurality of conductive vias coupling the first plurality of package terminals to the first plurality of fine pitch terminals; and

,

the second interconnection substrate comprises a second plurality of package terminals on the bottom surface and a second plurality of conductive vias coupling the second plurality of package terminals to the second plurality of fine pitch terminals.

16. An electrical assembly comprising:

a first IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a first through-silicon via terminating at a first top-side die terminal formed on the top surface of the first IC chip;

a first interconnection substrate with top and bottom surfaces and a plurality of fine-pitch terminals disposed on a top surface, the fine-pitch terminals of the first interconnection substrate being coupled in flip-chip connection with the bottom-side die terminals of the first IC chip;

a second IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a first edge-wrap connector extending from the bottom surface and terminating at a second top-side die terminal formed on the top surface of the second IC chip;

a second interconnection substrate with top and bottom surfaces and a plurality of fine-pitch terminals disposed on a top surface, the fine-pitch terminals being coupled in flip-chip connection with the bottom-side die terminals of the second IC chip; and

,

a first flexible circuit coupling the first top side die terminal and the second top side die terminal.

17. The electrical assembly of claim 16, further comprising a third or second? flexible circuit coupled between a third top side terminal on the first IC chip and a fourth top-side terminal on the second IC chip.

18. The electrical assembly of claim 16, further comprising a printed circuit board with a first plurality of circuit board terminals coupled to a second plurality of circuit board terminals through a corresponding plurality of circuit traces wherein;

the first interconnection substrate further comprises a first plurality of package terminals on the bottom surface and a first plurality of conductive vias coupling the first plurality of package terminals to the first plurality of fine pitch terminals; and

,

the second interconnection substrate comprises a second plurality of package terminals on the bottom surface and a second plurality of conductive vias coupling the second plurality of package terminals to the second plurality of fine pitch terminals.

19. An electrical assembly comprising:

a first IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a first edge-wrap connector extending from the bottom surface of the first IC chip and terminating at a first top-side die terminal formed on the top surface of the first IC chip;

a first interconnection substrate with top and bottom surfaces and a plurality of fine-pitch terminals disposed on a top surface, the fine-pitch terminals of the first interconnection substrate being coupled in flip-chip connection with the bottom-side die terminals of the first IC chip;

a second IC chip having top and bottom surfaces, a plurality of bottom side die terminals on the bottom surface, and a second edge-wrap connector extending from the bottom surface and terminating at a second top-side die terminal formed on the top surface of the second IC chip;

a second interconnection substrate with top and bottom surfaces and a plurality of fine-pitch terminals disposed on a top surface, the fine-pitch terminals being coupled in flip-chip connection with the bottom-side die terminals of the second IC chip; and

,

a first flexible circuit coupling the first top side die terminal and the second top side die terminal.

20. The electrical assembly of claim 19, further comprising a second flexible circuit coupled between a third top side terminal on the first IC chip and a fourth top-side terminal on the second IC chip.

21. The electrical assembly of claim 19, further comprising a printed circuit board with a first plurality of circuit board terminals coupled to a second plurality of circuit board terminals through a corresponding plurality of circuit traces wherein;

the first interconnection substrate further comprises a first plurality of package terminals on the bottom surface and a first plurality of conductive vias coupling the first plurality of package terminals to the first plurality of fine pitch terminals; and

,

the second interconnection substrate comprises a second plurality of package terminals on the bottom surface and a second plurality of conductive vias coupling the second plurality of package terminals to the second plurality of fine pitch terminals.

22. Apparatus comprising:

a printed circuit board;

at least two substrates flip chip mounted on said printed circuit board;

an integrated circuit chip flip chip mounted on each of said substrates, the integrated circuit chips having top surfaces; and

means for connecting signals between the top surfaces of respective of said integrated circuit chips.