Computer Memory Architecture for Hybrid Serial and Parallel Computing Systems

• US 20100287357A1
• Filed: 03/10/2010
• Published: 11/11/2010
• Est. Priority Date: 11/29/2005
• Status: Active Grant

• Current Assignee: XMTT, Inc.
• Original Assignee: XMTT, Inc.
• Inventors: Vishkin, Uzi Y.
• Granted Patent: US 8,145,879 B2
• Time in Patent Office: Days
• US Class Current: 712/207
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory.

Claims

1. An apparatus comprising:

a serial processor to execute instructions in a computing program primarily in serial;

a first, private memory to store data solely for use by the serial processor in executing the instructions;

a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory; and

a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions.

2. The apparatus of claim 1, wherein the second, local read-only memory of the at least one parallel processor may store updated data only when the updated data is also available in at least one shared memory module of the plurality of shared memory modules.

3. The apparatus of claim 1, wherein the second, local read-only memory is a local cache or register of the at least one parallel processor.

4. The apparatus of claim 1, wherein the serial processor, prior to a transition from a serial processing mode to a parallel processing mode, is to provide for a transfer of updated data from the serial memory to at least one shared memory module of the plurality of shared memory modules and to receive a corresponding acknowledgement from the at least one shared memory module that the updated data has been queued or committed for storage prior to any memory requests from the plurality of parallel processors.

5. The apparatus of claim 4, wherein the transfer of updated data from the serial memory to the at least one shared memory module is a data write back operation or a data write through operation.

6. The apparatus of claim 1, wherein the serial processor further is to broadcast a first signal to the plurality of parallel processors for substantially concurrent initiation of a parallel processing mode.

7. The apparatus of claim 1, wherein the serial processor, prior to a transition from a serial processing mode to a parallel processing mode, further is to broadcast a prefetch signal to the plurality of parallel processors to start prefetching data from at least one of the plurality of shared memory modules.

8. The apparatus of claim 7, wherein the serial processor further is to broadcast the prefetch signal to start data prefetching prior to a broadcast of a spawn command.

9. The apparatus of claim 7, wherein the prefetched data is stored in the second, local read-only memory of the at least one parallel processor of the plurality of parallel processors.

10. The apparatus of claim 1, wherein a transition from a serial processing mode to a parallel processing mode is performed when a spawn command is received by the plurality of parallel processors.

11. The apparatus of claim 10, wherein a plurality of threads are initiated substantially concurrently in the plurality of parallel processors upon the transition to the parallel processing mode.

12. The apparatus of claim 11, wherein a transition from the parallel processing mode to the serial processing mode is performed when a join command has been received by all spawned threads.

13. The apparatus of claim 1, wherein the serial processor further is to load data from the plurality of shared memory modules into the first, private memory upon a transition from the parallel processing mode to the serial processing mode.

14. The apparatus of claim 1, further comprising an interconnection network to transfer data between or among the plurality of shared memory modules, the plurality of parallel processors, or the serial memory.

15. The apparatus of claim 1, wherein the serial processor is a master processor to control a transition from a serial processing mode to a parallel processing mode.

16. The apparatus of claim 1, further comprising a broadcast network coupled to the serial processor and to the plurality of parallel processors, wherein instructions for the program are broadcast to the plurality of parallel processors via the broadcast network.

17. The apparatus of claim 1, wherein each parallel processor of the plurality of parallel processors comprises a thread control unit to execute instructions in the program.

18. The apparatus of claim 1, wherein the first, private memory is a level one cache memory.

19. The apparatus of claim 1, wherein the at least one parallel processor of the plurality of parallel processors is to write updated data to at least one shared memory module of the plurality of shared memory modules without writing to the second, local read-only memory or to a local cache.

31. The apparatus of claim 19, further comprising:

an interconnection network to transfer data between or among the plurality of shared memory modules, the plurality of parallel processors, and/or the serial processor; and

a broadcast network coupled to the plurality of parallel processors and to the serial processor, wherein the serial processor is to broadcast instructions for the computing program via the broadcast network to the plurality of parallel processors.

20. An apparatus comprising:

a serial processor to execute instructions in a computing program primarily in serial;

a first, private memory to store data solely for use by the serial processor in executing the instructions;

a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory; and

a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions;

wherein prior to a transition from a serial processing mode to a parallel processing mode, the serial processor is to broadcast a prefetching signal to the plurality of parallel processors to initiate prefetching of data from at least one of the plurality of shared memory modules.

21. The apparatus of claim 20, wherein the second, local read-only memory of the at least one parallel processor may store updated data only when the updated data is also available in at least one shared memory module of the plurality of shared memory modules.

22. The apparatus of claim 20, wherein the second, local read-only memory is a local cache or register of the at least one parallel processor.

23. The apparatus of claim 20, wherein prior to broadcast of the prefetching signal, the serial processor is to provide for a transfer of updated data from the first, private memory to at least one of the plurality of shared memory modules, is to receive a corresponding acknowledgement from the at least one of the plurality of shared memory modules that the updated data has been queued or committed prior to any memory requests from the plurality of parallel processors.

24. The apparatus of claim 20, wherein the serial processor further is to broadcast a parallel processing initiation signal to the plurality of parallel processors for substantially concurrent initiation of the parallel processing mode.

25. The apparatus of claim 20, wherein the serial processor is further to broadcast a pre-spawn command that causes pre-threads to be spawned to pre-fetch the data.

26. The apparatus of claim 20, wherein prefetched data is stored in the second, local read-only memory of the at least one parallel processor of the plurality of parallel processors.

27. The apparatus of claim 20, wherein the transition from the serial processing mode to the parallel processing mode is performed when a spawn command is received by the plurality of parallel processors.

28. The apparatus of claim 20, wherein a plurality of threads are initiated substantially concurrently in the plurality of parallel processors upon the transition to the parallel processing mode.

29. The apparatus of claim 28, wherein a transition from a primarily parallel processing mode to a primarily serial processing mode is performed when a join command is received in all threads.

30. The apparatus of claim 20, wherein the serial processor further is to load data from the plurality of shared memory modules into the first, private memory upon switching from the parallel processing mode to the serial processing mode.

32. A method of transitioning between a serial processing mode and a parallel processing mode in a computing system, the method comprising:

while in the serial processing mode, transferring updated data from a first private serial memory of a serial processor to at least one shared memory module of a plurality of shared memory modules;

receiving a corresponding acknowledgement from the at least one shared memory module that the updated data has been queued or committed for storage in memory, prior to any memory requests from a parallel processor of a plurality of parallel processors; and

broadcasting a first signal to the plurality of parallel processors for substantially concurrent initiation of the parallel processing mode.

33. The method of claim 32, further comprising:

prior to broadcasting the first signal, broadcasting a second signal to the plurality of parallel processors to initiate prefetching of data from the at least one shared memory module.

34. The method of claim 32, further comprising:

writing updated data to a second local memory of a parallel processor of the plurality of parallel processors only when the updated data is also available at least one shared memory module of the plurality of shared memory modules.

35. The method of claim 32, further comprising:

initiating a plurality of threads in the plurality of parallel processors upon the transition to the parallel processing mode.

36. The method of claim 35, further comprising:

transitioning from the parallel processing mode to the serial processing mode when a join command has been received by all spawned threads.

37. The method of claim 36, further comprising:

loading data from a shared memory module of the plurality of shared memory modules into the serial memory upon a transition from the parallel processing mode to the serial processing mode.

38. The method of claim 32, further comprising:

executing software instructions primarily in serial in the serial processing mode; and

executing software instructions primarily in parallel in the parallel processing mode.