COMPUTER SYSTEM AND METHOD OF CONTROLLING COMPUTER SYSTEM

• US 20100293314A1
• Filed: 05/13/2010
• Published: 11/18/2010
• Est. Priority Date: 05/14/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Komatsu, Hideaki, Kataoka, Masaki
• Granted Patent: US 8,909,835 B2
• Time in Patent Office: Days
• US Class Current: 710/262
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.

Claims

1. A computer system including an interrupt mask register, in which levels are set for respective interrupt processes, the computer system comprising:

designation means for designating a level to be set in the interrupt mask register and an address of a process to be called;

execution means for passing control to the address and assigning the interrupt mask register the designated level based on information designated by the designation means; and

means for disabling an interrupt as the execution means operates.

2. The computer system according to claim 1, wherein the level to be set in the interrupt mask register is set based on an operand following a predetermined instruction.

3. A computer system comprising:

an interrupt mask register;

level storage means storing a level for each interrupt;

execution means for shifting execution processes to the interrupt when acquiring a level for the interrupt, to which the execution process is shifted, from the level storage means, and for setting the acquired level in the interrupt mask register; and

means for disabling another interrupt as the execution means operates.

4. The computer system according to claim 3, wherein the execution means responds to occurrence of an interrupt.

6. The method of controlling a computer system according to claim 4, wherein the level to be set in the interrupt mask register is set based on an operand following a predetermined instruction.

5. A method of controlling a computer system, the computer system including an interrupt mask register and in which levels are set for respective interrupt processes, the method comprising the steps of:

designating a level to be set in the interrupt mask register and an address of a process to be called;

passing control to the address;

assigning the interrupt mask register the designated level on the basis of information designated in the designation step; and

disabling an interrupt during the execution step.

7. A method of controlling a computer system, the computer system including an interrupt mask register and in which levels are set for respective interrupt processes, the method comprising the steps of:

shifting execution processes to the interrupt;

acquiring a level for the interrupt, to which the execution process is shifted, from a level storage means;

setting the acquired level in the interrupt mask register; and

disabling another interrupt during the execution step.

8. The method according to claim 7, wherein:

the steps of shifting execution processes, acquiring a level for the interrupt and setting the acquired level in the interrupt mask register occur in response to occurrence of an interrupt.