Computer system and method of controlling computer system

• US 8,909,835 B2
• Filed: 05/13/2010
• Issued: 12/09/2014
• Est. Priority Date: 05/14/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kataoka, Masaki, Komatsu, Hideaki
• Primary Examiner(s): Myers, Paul R
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US12/779,456
• Publication Number:
  US 20100293314A1
• Time in Patent Office: 1,671 Days
• Field of Search: 710/305, 710/266, 395/735
• US Class Current: 710/266
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.

Claims

1. A computer system including an interrupt mask register, in which levels are set for respective interrupt processes, the computer system comprising:

designation means for designating a level to be set in the interrupt mask register and an address of a process to be called;

execution means for passing control to the address and assigning the interrupt mask register a designated level based on information designated by the designation means, wherein the execution order of the interrupt processes is prioritized based on the process to be called; and

means for disabling an interrupt as the execution means operates, such that influence from one or more instructions for a call, any other interrupt, and one or more exceptions is prevented while a value of an interrupt is changed so that a content of the interrupt mask register is not altered, wherein the means for disabling the interrupt includes a logic gate.

2. The computer system according to claim 1, wherein the level to be set in the interrupt mask register is set based on an operand following a predetermined instruction.

9. The system according to claim 1, wherein the logic gate includes an AND gate.

10. The system according to claim 1, further comprising a central processing unit (CPU) architecture that is modified so that a content of the interrupt mask register is directly changed based on a decoding result of one or more instruction decoders within the CPU.

11. The system according to claim 10, wherein the CPU architecture is configured to execute an instruction which concurrently executes a call of a process and a value change of the interrupt mask register, and to disable other interrupts during execution of the instruction to achieve atomicity.

3. A computer system comprising:

an interrupt mask register;

level storage means storing a level for each individual interrupt;

execution means for shifting execution processes to the interrupt when acquiring a level for the interrupt, to which the execution process is shifted, from the level storage means, and for setting the acquired level in the interrupt mask register; and

means for disabling an interrupt as the execution means operates, such that influence from one or more instructions for a call, any other interrupt, and one or more exceptions is prevented while a value of an interrupt is changed so that a content of the interrupt mask register is not altered, wherein the means for disabling or overriding the interrupt includes a logic gate.

4. The computer system according to claim 3, wherein the execution means responds to occurrence of an interrupt.

5. A method of controlling a computer system, the computer system including an interrupt mask register in which levels are set for respective interrupt processes, the method comprising the steps of:

designating a level to be set in the interrupt mask register and an address of a process to be called, wherein the execution order of the interrupt processes is prioritized based on the process to be called;

passing control to the address;

assigning the interrupt mask register the designated level on the basis of information designated in the designation step; and

disabling an interrupt during an execution step, such that influence from one or more instructions for a call, any other interrupt, and one or more exceptions is prevented while a value of an interrupt is changed so that a content of the interrupt mask register is not altered, wherein a means for disabling the interrupt includes employing a logic gate.

6. The method of controlling a computer system according to claim 5, wherein the level to be set in the interrupt mask register is set based on an operand following a predetermined instruction.

7. A method of controlling a computer system, the computer system including an interrupt mask register and in which levels are set for respective interrupt processes, the method comprising the steps of:

shifting execution processes to an interrupt;

acquiring a level for the interrupt, to which the execution process is shifted, from a level storage means;

setting an acquired level in the interrupt mask register; and

disabling another interrupt during an execution step, such that influence from one or more instructions for a call, any other interrupt, and one or more exceptions is prevented while a value of an interrupt is changed so that a content of the interrupt mask register is not altered, wherein a means for disabling the another interrupt during the execution step includes employing a logic gate.

8. The method according to claim 7, wherein the steps of shifting execution processes, acquiring a level for the interrupt, and setting an acquired level in the interrupt mask register occur in response to an occurrence of an interrupt.

12. The method according to claim 7, wherein the value of the interrupt mask register is changed by employing at least one of one or more extended CALL instructions and one or more extended software interrupt instructions.

13. The method according to claim 7, wherein a content of the interrupt mask register is directly changed based on a decoding result of one or more instruction decoders within the CPU.

14. The method according to claim 7, wherein atomicity is achieved by executing an instruction which concurrently executes a call of a process and a value change of the interrupt mask register, and by disabling other interrupts during execution of the instruction.