PHOTOVOLTAIC MODULES AND METHODS OF MANUFACTURING PHOTOVOLTAIC MODULES HAVING MULTIPLE SEMICONDUCTOR LAYER STACKS

• US 20100313952A1
• Filed: 06/08/2010
• Published: 12/16/2010
• Est. Priority Date: 06/10/2009
• Status: Abandoned Application

• Current Assignee: Thinsilicon Corporation
• Original Assignee: Thinsilicon Corporation
• Inventors: Rosenthal, Samuel, Stephens, Jason, Hussen, Guleid, Girotra, Kunal, Coakley, Kevin Michael
• Application Number:
  US12/796,039
• Publication Number:
  US 20100313952A1
• Time in Patent Office: Days
• US Class Current: 136/258
• CPC Class Codes: H01L 27/1421 comprising bypass diodes integrated or directly associated with the device, e.g. bypass diode integrated or formed in or on the same substrate as the solar cell
• CPC Class Codes: H01L 31/0236 Special surface textures
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/046 PV modules composed of a plurality of thin film solar cells deposited on the same substrate
• CPC Class Codes: H01L 31/0463 characterised by special patterning methods to connect the PV cells in a module, e.g. laser cutting of the conductive or active layers
• CPC Class Codes: H01L 31/076 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1824 Special manufacturing methods for microcrystalline Si, uc-Si
• CPC Class Codes: H01L 31/20 such devices or parts thereof comprising amorphous semiconductor materials
• CPC Class Codes: H01L 31/202 including only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/545 Microcrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A monolithically-integrated photovoltaic module is provided. The module includes an electrically insulating substrate, a lower stack of microcrystalline silicon layers above the substrate, a middle stack of amorphous silicon layers above the lower stack, an upper stack of amorphous silicon layers above the middle stack, and a light transmissive cover layer above the upper stack. An energy band gap of each of the lower, middle and upper stacks differs from one another such that a different spectrum of incident light is absorbed by each of the lower, middle and upper stacks.

Claims

1. A monolithically-integrated photovoltaic module comprising:

an electrically insulating substrate;

a lower stack of microcrystalline silicon layers above the substrate;

a middle stack of amorphous silicon layers above the lower stack;

an upper stack of amorphous silicon layers above the middle stack; and

a light transmissive cover layer disposed above the upper stack, wherein an energy band gap of each of the lower, middle and upper stacks differs from one another such that a different spectrum of incident light is absorbed by each of the lower, middle and upper stacks.

2. The photovoltaic cell of claim 1, each of the lower, middle, and upper stacks include an N-I-P junction of silicon sublayers.

3. The photovoltaic cell of claim 1, wherein the energy band gap of the upper stack is greater than the energy band gap of the middle stack and the energy band gap of the middle stack is greater than the energy band gap of the lower stack.

4. The photovoltaic cell of claim 1, further comprising a reflector layer between the lower and middle stacks, the reflector layer reflecting a portion of the light back into the middle stack and permitting another portion of the light to pass through the reflector layer and enter into the lower stack.

5. The photovoltaic cell of claim 1, further comprising a lower electrode between the lower stack and the substrate and an upper electrode between the upper stack and the cover layer, further wherein one or more of the upper, middle or lower stacks comprises a built-in bypass diode that vertically extends through the one or more of the upper, middle or lower stacks from the lower electrode to the upper electrode.

6. The photovoltaic cell of claim 5, wherein the bypass diode comprises a portion of the one or more of the upper, middle or lower stacks having a crystalline fraction that is greater than a remainder of the one or more of the upper, middle or lower stacks, the bypass diode conducting electric current between the upper and lower electrodes when the cell is reverse biased.

7. The photovoltaic cell of claim 5, wherein the bypass diode comprises a portion of the one or more of the upper, middle or lower stacks having a crystalline fraction that is greater than a remainder of the one or more of the upper, middle or lower stacks, the bypass diode conducting electric current between the upper and lower electrodes when the cell is shaded from the light and adjacent cells are exposed to the light.

8. The photovoltaic cell of claim 1, wherein the energy band gap of the upper stack is at least approximately 1.85 eV, the energy band gap of the middle stack is at least approximately 1.65 eV and less than the energy band gap of the upper stack, and the energy band gap of the lower stack is at least approximately 1.1 eV and less than the energy band gap of the middle stack.

9. The photovoltaic cell of claim 1, further comprising an upper electrode above the upper stack and a lower electrode below the lower stack, wherein a thickness of the upper electrode is based on a wavelength of the light that passes through the upper electrode.

10. The photovoltaic cell of claim 1, wherein the middle stack is formed from silicon or doped silicon without germanium (Ge).

11. A method for manufacturing a photovoltaic module, the method comprising:

providing an electrically insulating substrate and a lower electrode;

depositing a lower stack of microcrystalline silicon layers above the lower electrode;

depositing a middle stack of amorphous silicon layers above the lower stack;

depositing an upper stack of amorphous silicon layers above the middle stack; and

providing an upper electrode above the upper stack, wherein an energy band gap of each of the lower, middle, and upper stacks differing from one another such that a different spectrum of incident light is absorbed by each of the lower, middle and upper stacks.

12. The method of claim 11, wherein the lower and middle stacks each include an n-doped layer, an intrinsic layer, and a p-doped layer, the n-doped and intrinsic layers of the lower and middle stacks deposited at a temperature of at least 250 degrees Celsius with the p-doped layers of the lower and middle stacks deposited at a temperature of 250 degrees Celsius or less.

13. The method of claim 12, wherein the upper stack is deposited at a temperature of 220 degrees Celsius or less.

14. The method of claim 11, further comprising depositing a reflector layer above the lower stack of microcrystalline silicon layers and before the depositing of the middle stack of amorphous silicon layers, the reflector layer reflecting a portion of the light back into the middle stack and permitting another portion of the light to pass through the reflector layer and enter into the lower stack.

15. The method of claim 11, further comprising removing portions of the upper electrode to define photovoltaic cells and to electrically separate sections of the upper electrode in adjacent photovoltaic cells, wherein the removing operation forms a bypass diode extending through the lower, middle, and upper stacks from the lower electrode to the upper electrode in the photovoltaic cells.

16. The method of claim 15, wherein the removing operation increases a crystalline fraction of a portion of the lower, middle, and upper stacks to be greater than a remainder of the lower, middle, and upper stacks, the portion having the increased crystalline fraction forming the bypass diode.

17. The method of claim 15, further comprising conducting electric current between the upper and lower electrodes through the bypass diode when the photovoltaic cell having the bypass diode is reverse biased.

18. The method of claim 15, further comprising conducting electric current between the upper and lower electrodes through the bypass diode when the photovoltaic cell having the bypass diode is shaded from incident light and adjacent cells are exposed to the light.

19. The method of claim 11, wherein the depositing the upper electrode comprises depositing the upper electrode in a thickness that is based on a wavelength of incident light that passes through the upper electrode.

20. The method of claim 11, wherein the depositing the middle stack comprises depositing the middle stack of amorphous silicon layers without depositing germanium (Ge).